LMK03328: Crystal Input Interface

Shuji Ishiwata

Part Number: LMK03328

Hi Team

I have some questions about LMK03328.

1)Is there any difference in electrical characteristics between crystal input and clean external reference input inputs?
I think that both are the same if you margin the electrical characteristics. Is it right?

2)10.4.3 Crystal Input Interface (SEC_REF)"The programmable capacitors on LMK03328 can be tuned from 14 pF to 24 pF in steps of 14 fF using either an analog voltage on GPIO5 in soft pin mode or through I2C in soft pin or hard pin mode."
I have a question with the above contents.
In Soft pin mode, set with GPIO5. How to set in Hard pin mode?

Best Regards,
Ishiwata

over 5 years ago

0 Alan O over 5 years ago

TI__Mastermind 32575 points

Hello,

1. The external clock input modes (differential or single-ended on PRI/SEC_REF) and crystal input mode (SEC_REF only) are different, as shown in the electrical characteristics table. The crystal input uses an external crystal resonator with the built-in crystal oscillator stage, which has very low phase noise/jitter (less than 100-fs RMS jitter integrated from 12 kHz to 5 MHz). This crystal input provides excellent performance and could provide better power supply noise rejection compared to an external crystal oscillator.

2. The on-chip crystal load capacitance cannot be modified through the GPIO pins in Hard pin mode, since all GPIO[5:0] pins are used to select the start-up configuration from ROM. After start-up in Hard pin mode, it is only possible to control the crystal loading through I2C registers.

Regards,
Alan

0 Shuji Ishiwata over 5 years ago in reply to Alan O

Genius 5905 points

Hi Alan -san

I appreciate your reply.
I have an additional question.

1)Will there be a difference in output when inputting with crystal input and clean external reference input?

2)If control the crystal loading through I2C registers, Which register is used ?

Best Regards,
Ishiwata

0 Alan O over 5 years ago in reply to Shuji Ishiwata

TI__Mastermind 32575 points

1. If the external reference input clock RMS jitter is <= 100 fs rms (12 kHz to 20 MHz), then the output clock phase jitter should be as good as using the crystal input.
2. When R86[3:2] (MARGIN_OPTION) = 0x2, you can use R104 & R105 (XOOFFSET_SW) to set the crystal load capacitance. An example of the crystal frequency pulling vs. cap code (XOOFFSET value) characteristic is shown in Figure 6 of the following app note. Note that this curve is specific to the crystal trim sensitivity parameters and board design/parasitics.
www.ti.com/.../snaa281a.pdf

Regards,
Alan

0 Shuji Ishiwata over 5 years ago in reply to Alan O

Genius 5905 points

Hi Alan -san

Thank you for your support.

Best Regards,
Ishiwata

0 Shuji Ishiwata over 5 years ago in reply to Shuji Ishiwata

Genius 5905 points

Hi Alan -san

Thank you for contacting. Thank you for your support.
I have an additional question.

1)
"10.1 Overview
"The LMK03328 generates eight outputs with less than 0.2-ps rms maximum random jitter in integer PLL mode
"and less than 0.35-ps rms maximum random jitter in fractional PLL mode with a crystal input or a clean external
"reference input.

With regard to the above description, is it OK to understand that the same performance as crystal input can be achieved when clean external reference input is used?
It is an understanding that using crystal input is the following advantages.

"10.3 Feature Description
" When the PLLs operate with the crystal as their reference, the output frequencies can be margined based on
" changing the on-chip capacitor loading on each leg of the crystal.

2)
"p.41 GPIO4 pin should be tied to VDD and GPIO5 pin should be floating when device is operating in soft pin"
About Table 4, I think that there is no mention of capacity setting. Is it listed somewhere? Or maybe I do not understand?

3)
LDO of "10.3.1 Device Block-Level Description(p.30)" and "Figure 62. Structure of AC-LVDS, AC-CML, and AC-LVPECL Output Stage(p.48)"
Is my understanding correct that it adapts without register setting?
And will the same power supply quality be used even when using the input(primary(6pin,7pin)and secondary(10pin,11pin)) terminal?

Best Regards,
Ishiwata

0 Alan O over 5 years ago in reply to Shuji Ishiwata

TI__Mastermind 32575 points

1. Yes, it is possible if the reference input clock jitter is considerably lower than the PLL output clock jitter specification.
2. The nominal load cap is 9 pF, per electrical spec table 8.7 in the datasheet.
3. Yes, the customer does not need to configure any registers for the internal power supply regulators to the different device blocks since it is handled internally. The only exception is 1.8-V LVCMOS output on OUT[0:7] ports expects its VDDOx supply to be 1.8 V. The primary and secondary input blocks have internal power regulation and are powered through the VDD_IN supply pin.

Regards,
Alan

0 Shuji Ishiwata over 5 years ago in reply to Alan O

Genius 5905 points

Hi Alan -san

Thank you for contacting. Thank you for your support.
I have an additional question about your answer(3).

"The only exception is 1.8-V LVCMOS output on OUT[0:7] ports expects its VDDOx supply to be 1.8 V."

The above answer is a specification that the potential when OUT [0: 7] is LVCMOS output is 1.8 V.
Therefore, is it OK to assume that the voltage used for LDO is VDDOx power supply 3.3 V, for example?

Also, is there any difference between using primary and secondary ports since it is output from OUT [0: 7] using the power supply of LDO generation after input?

Best Regards,
Ishiwata

0 Alan O over 5 years ago in reply to Shuji Ishiwata

TI__Mastermind 32575 points

The LDO is used for VDDOx of 2.5 V or 3.3 V, and is effectively bypassed for VDDOx of 1.8 V.

There is no difference between using primary and secondary ports in terms of power supply noise regulation.

Alan

Clock & timing

Clock & timing forum

LMK03328: Crystal Input Interface