LMK04906: PLL1 Lock detect issue.

Hello, 

We have CLKIN freq as 25MHz and OSCin freq as 80MHz. 

We have set PLL1_R = 5 and PLL1_N = 16. 

so, PDF = 5MHz. 

We are getting an issue of PLL1 lock detect. The Lock detect signal is seems like a continuous clock with 25% duty cycle. 

I have set the PLL_LOCK_Window parameter as 40ns (max.), and the PLL1_DLD_COUNT settings as 1(min), still the PLL1_Lock detect is not continuous '1'. 

Please let me know, What can be the problem? 

Thanks and Regards

Tarang Jindal