• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 20 subscribers
  • Views 287 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04826: PLL1

Layne Jakahi
Intellectual 820 points
Part Number: LMK04826

2146.LMK04826B PLL1 LOCKING PROBLEM.pdf

Hi, guys,

I am using PLL1 LMK04826B's CLKIN0 as ref input and OSCin as the external VCO feedback input.

Our PD frequency is 1.536MHz.

We just found out a very odd problem.

Let's say I have a master card that generates ref clock and a slave card that receives the ref clock. the ref clock from the master card is fed into CLKIN0 differential pins of LMK PLL1 of slave card.

we are monitoring the slave card PLL1 R and N divider output on the oscillator scope when PLL1 locks. By keeping the same slave card, but swapping different master cards, we get different relationship between the R divider and N divider output on slave card PLL1, which will be attached during this post.

This is very abnormal since the whole purpose of Phase lock loop is to make R divider and N divider phase relationship constant.

I am aware of that if there is a leaky loop filter capacitor or leaky VCO on PLL1, the phase may not be aligned exactly between R and N divider output, but the phase offset should be constant if I keep the slave card the same。

By the way, We are feeding in a ref clock of 98.304Mhz, it is pulse width modulated ref clock. The pattern is three highs one low and then one high three lows, but the rising edge rate is constant at 98.304Mhz. both the R and N divider is 64, which comes to the PD frequency of 1.536MHz.  

Attached you will find pictures of our experiment in the pdf file.

Thank you so much for your help, we have been stuck on this for a couple of days and run out of ideas to try.

  • 0
    TI__Mastermind 28540 points

    Hello Jakahi,

    You mention three different masters lead to different phase offsets in the slave.  Are the masters locked to the exact same frequency?  One thing I can think of is, if the if the Vtune of the VCXO on the slave LMK04826 changes, the dynamics of charge pump output could very ever so slightly along with the leakage current into the VCXO.

      - For CP, the charge pump current could have slight variation as illustrated in section 8.1 of datasheet.

      - For leakage, with higher Vtune voltage, leakage current into VCXO can increase.  Note leakage of the PLL1 CP is max 5 nA for Vtune 0.5 V to Vcc - 0.5 V, which is very low.

    For each of these cases is the PLL1 Vtune voltage different?  Now if the masters all had the same frequency source (0 ppm error).  Then all the VCXOs of the slaves should have the same Vtune voltage and the above doesn't explain, but it's not clear to me if this is the case.

    Phase variation based on leakage from VCXO can be minimized/eliminated by placing a unity gain op-amp before the Vtune input.  I don't know if this is something you could try.  What's the input impedance of your VCXO?  100k ohms range or 1 Mohms type range?

    I don't expect and issue with your duty cycle modulated clock.  Provided the rising edges are at the period of the 98.304 MHz, to my recollection - that should work fine.

    Layne Jakahi said:
    This is very abnormal since the whole purpose of Phase lock loop is to make R divider and N divider phase relationship constant.

    It is making the phase relationship constant but it is different in your three cases, in all cases the frequency has 0 error.  When the PLL makes the phase constant, then d(phase)/dt = 0 therefore there is 0 frequency error.

    73,
    Timothy