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CDCVF25081: PLL Bypass mode

Part Number: CDCVF25081

We need a zero delay buffer in the clock path normally. However the zero delay buffers have a min frequency requirement that doesn’t work out for JTAG testing.

I noticed that this part when the S2 pin is a 1 and the S1 pin is a 0 bypasses the PLL and just switches the reference clock input to the output.

We might be able to use this capability when in JTAG test mode. This way we can toggle the clock at a slow JTAG testing rate.

So my question is when the part is in PLL bypass mode can the ref frequency input be toggled at a slow rate that is below the min frequency when the part is in PLL mode.

The datasheet doesn’t specifically state this but does specify a delay of 2.5 to 6nsec tplh which is fine for JTAG testing when the part is in PLL bypass mode.

Best Regards, -Tim Starr on behalf of WM@FL

  • Hi Tim,

    I think we can tolerate a few MHz but without guarantee. However, I doubt if the part can support kHz clock. As you can see in Figure 7 of the datasheet, the supply current drops sharply when the clock frequency is a few MHz.