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TINA/Spice/NE555: NE555

user3731939
Prodigy 50 points
Part Number: NE555
Other Parts Discussed in Thread: TINA-TI, , LMC555, TLC555, TLV906X

Tool/software: TINA-TI or Spice Models

Hi, I want to confirm the frequency divider design circuit with NE555. In NE555 datasheet, page12, figure 15, it says refer to basic circuit in figure 9. So what is the value of  resistor "RL" in figure 9, page 10? Could you please clarify for this frequency divider circuit?  I simulate the circuit in Tina, the input is PWM signal with 10kHz, however, the output is not PWM signal.  I attached the Tina file in this community. Thanks for your support.Noname1.TSC

  • 0
    TI__Guru*** 139956 points

    Hello User,

    RL only affects VOH (Output High Voltage) often it can be omitted. The input signal must be high duty cycle as seen in figure 15 or it may be AC coupled like the attached Tina file. The output signal will also be high duty cycle but not the same duty cycle as the input. The input duty cycle is not preserved in the division process.

    The basic concept is that the 555 timer will ignore (not restart timing cap to zero) when new trigger inputs occur while already doing a cap charge cycle. Run an AC analysis transient to see this happening. (I added a cap ramp measurement)

    10kHz to 5kHz.TSC

  • 0 in reply to Ron Michallick
    Prodigy 50 points

    Thanks for your clarification. From your explanation, it seems 555 can not keep duty cycle when it is used as frequency divider. However, I want to further confirm with you that I want to keep the duty cycle, just change the PWM frequency. For example, the input signal is PWM with 90% duty cycle, 10kHz. The output will keep duty cycle no change and frequency can be changed to 5kHz.   Can I use 555 timer for this design? Or do you have any recommended design? Thank you.

  • 0 in reply to user3731939
    TI__Guru*** 139956 points

    I see two ways to tackle this problem.

    1) Convert 10 kHz duty cycle to a DC voltage value then make a 5 kHz triangle wave generator and use a comparator to generate 5 kHz as similar duty cycle using the saved DC voltage. This 5kHz will not be synchronised to the 10 kHz input and the response time will be slow (lag) or there will be a lot of duty cycle jitter in the 5 kHz signal (but faster). Could be implemented with one quad op amp.

    2) Double the (low or high time) of one 10 kHz pulse period to be the 5 kHz pulse width in real time and do it again using every alternate 10 kHz period.  This method is quick response , but it ignores every other 10 kHz period. So it preserves the duty cycle  5,000 times per second. This solution is more complicated. One monostable timer runs for 150us to block out every other 10 kHz input pulse.  The input pulse width charges a capacitor (C3) then the capacitor is discharged at the same rate until charge is gone. This doubles  the output pulse width. The output frequency is halved so the duty cycle is preserved. This require two more TLC555 (or LMC555) timers used as R/S latches. The other amp op is used as a comparator; better response time (better duty cycle accuracy) would be achieved if replaced with a real comparator.  This new circuit is lighted tested in simulation only; it is not a proven design.

    10kHz to 5kHz PWM.TSC

  • 0 in reply to Ron Michallick
    Prodigy 50 points

    Hi Michallick,

    Thanks for your suggestion. I would like the first way to solve the problem. My need is, the input PWM signal is 130kHz, 3V, 90% duty cycle or 10% duty cycle( input signle has two duty cycles). I need to keep the duty cycle no change and change the frequency to 1kHz. 

    I want to use a RC filter to filter the 130kHz , 90% duty cycle PWM signal, then get 2.7V DC signal.  Then can use NE555 to generate a 1kHz, 50% duty cycle, 3V signal, and connect an amplifier as an integral circuit to generate a 1kHz with 3V triangle wave.  And use a comparator to compare the 2.7V DC signal and 3V,1kHz  triangle wave, then get 1kHz, 90% PWM signal.  Would you please help to confirm this design? The power can use 5V and 3V.   Actually, I have some issues when I simulate to generate the triangle wave.  Low cost chip is prefer in the design.  Thanks for your help.

  • 0 in reply to user3731939
    TI__Guru*** 139956 points
    This is a big change from the first request of a 2:1 frequency reduction where duty cycle was analog. I'll present an idea on Tuesday.
  • 0 in reply to Ron Michallick
    TI__Guru*** 139956 points

    Here is a circuit that accepts 3V at 10% or 90% duty cycle at high frequency (130kHz) and produces 10% or 90% duty cycle at 1kHz.  The only side effect is that the sudden input change between 10% and 90% input can create one cycle that is neither 10% nor 90%.  To fix that would require sampling input duty cycle (after a comparator) using a D flip flop and using Q output for the ramp comparator. It runs from 3V supply so use LMC555 or TLC555. I use a TLV906X as a comparator. It is better to use a comparator instead.

    130k to 1k (digital) TLC555 TLV906X.TSC