The LVDS clock output from CDCI6214 is incorrect

user5214477

Part Number: CDCI6214

Hi,

I use CDCI6214 provide clock for FPGA,and Ouptut Format is LVDS 3.3V.

But the output clock is incorrect,Including peak, jitter and frequency of waveform.

This is waveform of Channel 2; My target frequency is 100MHz and the output buffer format is LVDS_3.3V.

This is waveform of Channel 3; My target frequency is 90MHz and the output buffer format is LVDS_3.3V.

This is waveform of Channel 4; My target frequency is 90MHz and the output buffer format is LVDS_3.3V.

The circuit diagram is as follows：

RC15 and RC18 is removed. RESETN is connected to MCU.

I don't know what the problem is or what to do. Someone can help me.

0 Dinesh Jain over 4 years ago

Hello,

I'm assuming that you are providing LVCMOS input to Pin #1. Please make sure that you enable Input CMOS buffer (Page#60, Table 38 of the d/s).

You would also need 100ohm differential resistor across REFCLKP and REFCLKN pair for LVDS to function properly.

Let us know if it works.

Regards,

dinesh.

0 user5214477 over 4 years ago in reply to Dinesh Jain

Hello,

Thanks for your reply.

I use CDCI6214 provide clock for FPGA's GTX,

The schematic diagram of the clock receiver is as follows.

And I added terminal resistance outside the receiving end of another circuit board, but it still didn't improve.

Regards.

0 user5214477 over 4 years ago in reply to Dinesh Jain

Hello,

Thank you very much.

Although the output waveform of CDCI6214 does not change on the oscilloscope, it can be used by the FPGA and the PLL of the FPGA can be locked.

The differential clock output from CDCI6214 can be used normally by the FPGA.

Regards

0 Hao Z over 4 years ago in reply to user5214477

Hello,

Has your problem been resolved? If so, please close this thread. Otherwise, let me know if you need further assistance.

Regards,

Hao

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