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Part Number: CDCE62002
Tool/software: WEBENCH® Design Tools
The part is CDCE62002,the input frequency is 37.125MHz(LVCMOS),the output frequency is 74.25MHz(LVDS)；
Designing the loop filter，Using the same RC filled into Loop filter Tool and WEBENCH Designer，but the different phase margin、loop bandwidth output，which is the best？
It is better to configure the loop filter for your application by following the procedure from this e2e post. I have pasted the procedure below for reference: https://e2e.ti.com/support/clock-and-timing/f/48/p/769060/2844477#2844477
Here is a procedure for designing a loop filter using the CDCE62005 EVM GUI:
I hope this information helps.
To design your own Clock Tree solution, visit WEBENCH Clock Architect !
More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html
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In reply to Lane Boyd:
My confusion is ：the same R2、C1、C2 input，but the different output（phase margin、loop bandwidth）between "Loop Filter" in CDCE62002 EVM GUI and WEBENCH Designer，which one is more accurate？pictures above show the detail parameters
In reply to lin huang:
Thank you for the clarification, I misunderstood your original question.
The WEBENCH result should match the GUI calculation once you input the VCO Gain.
the output are same once I input the VCO gain
thank you very much
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