CDCM6208: PLL lock issue

Hi Hoa,

Thanks for the response, we have checked the input clocks and it appears clean. 

Let me elaborate the scenario. 

Previously we were using Stellaris LM3S2D93 controller to configure the same CDCM IC. Stellaris part  was running at 16Mhz .In this case CDCM Ic is responding as expected. PLL is getting locked.

Presectly CDCM IC is same but we are trying to configure IC through TIVA C, TM4C1294NCPDT. Tiva is running at 25MHz. Here we are seeing the issue.

Please guide me to narrow down the issue.

Thanks and Regards,

Janardan M

Hi Janardan,

It seems like this might be due to SPI clock speed according to your description. Is there a way to reduce the SPI speed on your new controller? Also, with LM3S2D93 and  TM4C1294NCPDT, are you passing the same registers in the same sequence to CDCM6208?

Regards,

Hao

HI Hao,

The sequence in which CDCM is configured remains same for both the controllers.

As mentioned earlier 2 CDCM ICs on board are working as expected. 3rd CDCM IC I am able to write and read back the registers but PLL is not getting locked , so I am not seeing that to be SPI related issue.

But I will further reduce clock speed and test the setup and update on observation.

Thanks,

Janardan 

Hi Janardan,

When there's loss of lock while the register setting is correct, the problem is often due to failure of input detection. Meaning that it fails to detect input signal due to input distortion caused by impedance mismatch and reflection. I suggest trying different input formats and switching between PRIREF and SECREF if possible. I assume that you are not using crystal, correct?

Regards,
Hao

Hi Hao,

The issue is not yet resolved. We had paused this work due to some reason and resumed the activity now.

The CDCM IC I was discussing about was working when programmed through Stellaris based controller. We checked the impedences , everything appears fine.

Now change is Stellaris based controller is replaced with TIVA based controller. In our board we have 3 CDCM ICs. out of these 2 are working fine when programed through TIVA.

For third CDCM IC the SPI read/writes are proper , also for a small duration of time PLL is getting locked and again the line becomes low. 

What would the possible issue?

Thanks,

Janardan  

Hi Janardan,

I'm afraid I can't think of any reason if the three ICs have the same initialization sequence, schematic and etc. Can you swap the locking ICs with the not-locking IC to check if the problem follows the chip or external environment?

Regards,

Hao