This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • TI Thinks Resolved

LMX2615-SP: programming questions (2)

Intellectual 2085 points

Replies: 1

Views: 58

Part Number: LMX2615-SP

Team,

Can you help with the below:

We currently program the PLL in this fashion,

1) 114 registers are sent to the PLL for "Default frequency setup" as stated in 7.5.1 Recommended Initial Power-Up Sequence. (Recieved these register settings From TICSPRO application)

2) Each frequency change after the default settings is 7 registers containing num, denom, n divider, and r0 are sent as recommended by 7.5.2 Recommended Sequence for Changing Frequencies. the 7 registers are sent in descending order, just like the initial boot sequence.

____________________________________________

 

1) Are there any other registers or register settings that that we should be changing for any reason during run time, after default settings have been set up

2) We have applications that have wide frequency bands, where VCO Core changes are needed during runtime, what registers should be changed if a VCO core is changed during runtime

3) Is there a minimum time that should be given between changing frequencies, or can commands be sent back to back at 2 MHZ

4) Is there a minimum time that should be given if we do change VCO Cores during runtime.

5) Do the Registers ever get changed by an SEE or any other effect after they are set inside of the PLL? Should I send a refresh 114 registers every once in a while? Or is this what the PLL watchdog was meant to troubleshoot?

6) Would the PLL watchdog catch a register change as talked about in 5?

7) Does the PLL watchdog occur if lock detect is not locked?

8) Is there a status update on recommended settings for TICSPRO on windows 10 machines.

  • Hi Michael,

    1. No

    2. the calibration routine will take care of it, you don't need to do extra

    3. you have to reserve time for vco calibration + analog loop lock time. Calibration time is in the range of 100µs, it could be longer or shorter, depending on frequency setting. Analog lock time depends on loop bandwidth.

    4. same as 3. above.

    5, 6, 7. The watchdog is used during VCO calibration. It will re-start calibration if calibration takes longer time than the watchdog timer. Register values remain unchanged. If you have made RECAL_EN pin HIGH, calibration will be re-started again if the device loses lock for a pre-defined time specified by LD_DLY.

    8. The "Default mode" setting in TICS Pro is just an example, it is not a recommended setting. People should change the configuration based on their system requirement.

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.