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CDCI6214: 50% failure rate on the FOD

Part Number: CDCI6214
Other Parts Discussed in Thread: CDCE6214-Q1

I'm running into a bizarre problem. When I use the integer output divider, 100% of the chips work. When I use the fractional divider, on about half of the chips (6 out of 12 tested), the output is off frequency and noisy. An oscilloscope shows almost noise-like glitches on the output, like the input signal to the divider was noisy. Has anyone experienced this?   

I replaced the chip on one of the bad boards, and now it works great. Any helpful suggestions? Do I really have a 50% failure rate on these chips? 

  • To make things even more strange, I tried using an adjacent channel's fractional divider. Two of the units that failed work just fine when the adjacent channel's modulator is used.

  • Another interesting data point: freeze spray. On a bad unit, freeze spray (i.e. cooling the chip) drastically affects the output. The frequency was never correct, but it seemed to snap to 2 bad frequencies at specific temperature ranges as it cooled, and be quite noisy in between. I tried both shielding the chip and adding noise to the power supply. No effect in either case. 

  • Hi Justin,

    We are investigating this issue internally right now. Like you may have seen, channel 1 FOD output sometimes gives incorrect frequency while IOD and channel 2 are working properly. 

    For now please avoid using CDCI6214 FOD if possible. CDCE6214-Q1 is a pin-pin compatible part with CDCI6214. It has fractional PLL.

    Regards,
    Hao

  • Thanks. This is a sub-optimal solution as we already have units built, but I will look at the CDCE6214-Q1.

  • With the CDCE6214-Q1 (which looks mostly perfect by the way), quick question:
    How does one produce a 93.4 MHz output?

    I ask because the architecture is a 2.35 - 2.6 GHz VCO, followed by a divide-by [4/5/6], followed by a divide by N.

    You can output VCO / 25 = 94-104 MHz, and VCO / 28 = 83.9 - 92.9 MHz

    Can you stretch the VCO to, say, 2.335 to 2.616 GHz?

  • FYI: Our application requires a very flexible clock from 60 - 102 MHz.

  • Hi Justin,

    I did the math and agree with you that 92.9 to 94 cannot be covered. I can't say that stretching the VCO is an option. This is actually why I let Lauren ask your frequency plan previously, because I was worried that you happen to need frequencies in the gap. I'll see if the designers can comment on this.

    Regards,

    Hao

  • After playing with the CDCE6214-Q1, I'm going to say that stretching the VCO frequency a hair to cover all frequencies up to 100 MHz is probably just fine. Also, future users of the CDCE6214-Q1, don't forget to set the MASH order to 3 or you'll have ugly integer boundary spurs :)

  • Hi Justin,

    This is good. I've also got the feedback from designer. After checking the histogram of VCO min/max data, The upper side has a great margin up to 2.8GHz. However, the designers shifted the VCO frequency down a little bit to re-centered it. Therefore, There will be some VCO frequency shift in the new silicon (the final silicon for RTM). We can only know the frequency range of VCO on new silicon after re-measuring the histogram. Still, stretching the VCO a little bit to fill the gap up to 102MHz shouldn't be a problem, because there'll probably be plenty of margin on both sides with the final silicon.

    Regards,
    Hao