This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04832EVM: Can not setup LMK04832 operate in Dual Loop mode

Part Number: LMK04832EVM
Other Parts Discussed in Thread: LMK04832

Dear Sir ! I use LMK04832 device in my board and need to configure it operate in Dual loop mode. But i can not get PLL2 DLD (Status_LD2) lock. When i tried to use in single loop mode, the PLL2 DLD (Status_LD2) locked, and i got the correct outputs frequency. Please look into my setting and give me some recommendations ! thank you ! 

LMK04832_single_PLL2.tcs

  • Here is my setting for LMK04832 in dual loop mode :

    LMK04832_dual_loop_mode.tcs

  • Hello Duc,

    The only difference between these tcs files is the state of the PLL2_RCLK_MUX. Since PLL2 indicates lock when referenced to CLKin1, but not locked when referenced to OSCin, this suggests the problem is with PLL1 or the VCXO. Is PLL1 locking in the dual loop configuration?

    Regards,

  • Hello ! Thank you for your reply ! Yes, i think problem is with PLL1 or VCXO. But in my board has not indicator (Led) of PLL1 lock, so i can not check  locking of PLL1. I have measured pin RF_OUT of VCXO (122.88MHz) and pin +VDD  (+3.3V). Now i have no idea for trying. Can you look into my schematic of LMK04832 and give me suggestions, please !  I think about pin RESET/GPO (in my board this pin pull-down to GND directly), and pin SYNC is floating (beacause i dont need synchronize multi LMK04832s)

  • Hi Duc,

    It looks like you have a connection for LMK LD2. For debugging, you can change the value of PLL2_LD_MUX register to output PLL1 DLD, and confirm if PLL1 is locking.

    For the schematic, I notice that OSCin_N terminal is connected directly to ground. OSCin_N should be connected to GND through a 0.1µF capacitor when driven single-ended, just like for single-ended CLKinX pins, to preserve the common mode biasing. An issue on the OSCin input would explain the behavior you described (PLL2 locks when using CLKin1 as an input, but does not lock when using OSCin as the input). That being said, check if PLL1 is locking first before making this modification. If PLL1 is locking with OSCin_N directly connected to GND, we need to consider alternate explanations.

    Regards,

  • yes, i changed PLL2_LD_MUX register to PLL1 DLD and PLL1 until is not locked. But when i using OSCin as input for single PLL2 i see PLL2 Locked(but not stable, indicator led light on and off). Here is my new setting:

    LMK24M576_input_single_PLL2.tcs

  • Hi Duc,

    If you are not getting stable lock for PLL2 with the signal fed directly to OSCin as well, that suggests it is the OSCin_N pin tied directly to ground. Please update OSCin_N to be connected to ground through a 0.1µF capacitor instead.

    Regards,