LMK03328EVM: PLL is not locking

I am inputting a LVDS 10.949297MHz clock on PRIREF.  I have various frequency tables loaded into the EEPROM to get 44MHz (4x), 88MHz (8x), and other frequencies (based on PLL1).  I'm using TICS Pro, PRIREF = Diff Input, Max Gain, DIFFTERM_PRI, and AC_MODE_PRI.  The clock at PRIREF looks pretty good and is a 422mVpk-pk, 1.35ns risetime, ,829ps fall-time.  I measured this with a differential probe.  I don't believe the PLL is locking for AC-LVDS outputs (from PLL1) as only the desired frequency is displayed for a short period of time and seems to be fluctuating.  I do have an output as CMOS(+/-) sourced from PLL2 which seems to be fine.  I originally checked out my design with the LMK03328 EVM but CMOS(+/-) signal ended input clock and outputs.  I then copied those settings changing the input & output to LVDS accordingly and loaded that into the PLL on my PWB.  I did look at this thread http://e2e.ti.com/support/clock-and-timing/f/48/t/761411?LMK03328-How-to-debug-PLL-Loss-of-Lock in addition to looking at section 10 in the datasheet and adjusting some of the register settings according.  Changed R29.7, R51.7 to 1.  Changed REFSEL from Low to Hi.  Changed R50.3 & R50.1 from 1 to 0.  Changed R50.2 and R50.0 from 0 to 1.  Changed R50.7 from 1 to 0.  Changed R29.3 from 0 to 1.  The new load into the EEPROM produced the same results where I'm not getting a stable LVDS output clocks.  I don't understand why the LMK03328 is not locking for the LVDS outputs.