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LMK05028: One question about LMK05028
Part Number: LMK05028
I want to using LMK05028 DPLL1 to lock with 1PPS from REF_IN2 to generate clock 156.25MHz and DPLL2 lock to VCO1 FB to generate clock 122.88MHz
I choose DPLL2 mode is 2 loop TCXO, APLL, input reference is VCO1 FB but when I run script The TICS Pro said Run cancelled. DPLL(2) missing input assignment.
How to set up adjustment to solve this problem?
This is a current issue I'm working on correcting and make an updated TICS Pro release. Do you have a time line for your setup?
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In reply to Timothy T:
We will have first prototype in Oct.
Also, I have another question. at initial lock to 1PPS the output frequency jump back and fourth a lot. it jump up to 156.43MHz, 156.06MHz then it start run around 156.25MHz with small step until lock.
Does the big jump frequency is normal or i need ajust something?
Is it fastlock behavior of the chip. Can i disable fastlock and have a clamp the Max, Min of output to avoid big diviation.
In reply to PHI TU:
I don't expect big jumps with a lock to 1 PPS. What is your loop bandwidth? With a 1 PPS input, your loop bandwidth should generally be 0.1 Hz or less.
My REF LBW is 0.02Hz and TCXO LBW is 200Hz
I record a video, please take a look the link below.
It start at 4 Sec, I press PDN button, it keep jumping about a minute then adjust with small step until lock.
I was able to review the video. Can you confirm a clean signal is getting through by probing the REFx Monitor div out, div-by-2 (for example for STAT0 pin output set 0x2e = 0x0d.
You should see a 0.5 Hz signal.
Yes. I was setup REFx Monitor div out, div-by-2 and TDC Feeback out to STAT0, STAT1. It blinking at 0.5Hz, after lock it blink same phase
Could you share a save file (TCS file) that I can try to reproduce your results. I would need to get back with you next week on this.
I attach the TCS file
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