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LMK00105: D/S Question & Configure as Inverting Buffer?

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Replies: 6

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Part Number: LMK00105

Team,

  1. Based off the following lines of the datasheet, the output voltage supply cannot exceed the core voltage supply. What are the consequences if it does?
  2. Is there a way to configure this part as an inverting buffer while using a single ended input? Can this be done by using the recommended input configuration in the datasheet, but feeding the input clock to the CLKin- pin?

Thank you.

  • A1. One serious potential consequence could be permanent damage to the device.

    A2. Yes, driving the CLKin- input rather than CLKin+ will invert the output.

    Kind regards,
    Lane

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Lane Boyd:

    Are there other consequences for out of spec output supply voltage? Degradation of output signals, for example?

  • In reply to zack xing:

    Yes, output degradation is possible. This is operating condition is outside of the recommended operating conditions. Even if the device is still functional, you may not achieve the performance guaranteed in the electrical tables.

    Kind regards,
    Lane

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • We will update the design and replace part, but for debugging of the current board.

    For A1 below, what other consequences could occur – signal integrity issues?

    What would the expected output voltage be when the VDD = 2.5v & VDDO = 3.3v?

     

    A1. One serious potential consequence could be permanent damage to the device.


  • In reply to Richard Cundiff:

    Are you facing issues with the device in your design? What do you observe?

    Kind regards,
    Lane

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Lane Boyd:

    There are ESD DIODES connecting VDDO to VDD. If VDDO exceeds VDD by 0.8V, these diodes will turn on and start to conduct current. There is a 1K resistor which will limit the current. At 3.3V and 2.5V, that is 0.8V, therefore there will not be much current.

    As far as the output voltage, 2.5V will not completely turn off the PMOS and will result in high shoot-through current, and as a result the output low voltage will not be 0V. It may be low enough for the application, but will not be guaranteed to work properly. Bottom line, is that the device won’t blow up, but may not function properly.

    Kind regards,
    Lane

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html