• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 20 subscribers
  • Views 174 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04828: DCLKOUT Offset Voltage Variation

Santhana Krishnan T L
Prodigy 170 points
Part Number: LMK04828

Hi everyone,

I am using LMK04828B PLL in my application for generating three JESD reference clock of 200MHz to FPGA.

These three clock signals are taken from DCLKOUT0, DCLKOUT2 and DCLKOUT12 differential pins.

I have configured these three clock's format as LVDS in internal registers. These Clocks are connected to FPGA through AC coupling capacitor (0.01uF).

While probing I observed the offset voltage of 1.27V in all the three Ouput Clocks at the PLL output pins. While measuring after capacitor(FPGA end), 1.27V offset voltage was removed for the clocks DCLKOUT0, DCLKOUT2 alone. Still Offset voltage of 730mV is observed  in the capacitor (FPGA end) of clock DCLKOUT12.

Is any termination circuit needed in receiver end for remove this offset voltage of 730mV?

With Regards,
Santhana Krishnan T L

  • 0
    TI__Mastermind 28540 points

    Hello Santhana,

    The FPGA should be self biasing the input, that is why you see a different input DC voltage.  In fact, I would also expect the other inputs to self bias the input, if not - you may have some issues as need to DC couple.  Ensure the LVDS Vcm of ~1.25 V is proper for your FPGA configuration.

    As a side note, when AC coupling LVDS and HSDS with LMK0482x, you should also place 560 ohm resistor across the outputs close to output on LMK side of capacitors.

    73,
    Timothy