Other Parts Discussed in Thread: LMK04832, ADS62P49, DAC3283
Hello, I am working with an Abaco FMC150 reference design and am having problems synchronizing multiple CDCE72010 devices with each other.
- Each PLL is on a separate circuit board, and has a separate 800 MHz oscillator connected to the VXCO pins.
- Each PLL has a 10 MHz reference clock (same source) connected to the PRI_REF pins.
I can see that the multiple PLLs are achieving lock, and their generated clocks are phase-locked with each other, however:
1) Even though the generated clocks from PLL-1 and PLL-2 are phase-locked, the output divider counters are out of sync, and thus the generated clocks are not phase aligned.
- If I toggle the RESET pin synchronously on the PLL's, I can get the phase on PLL-A's clocks to be in line with PLL'Bs clocks some of the time other times, the output clocks from A to B are 180 degrees out of phase.
2) When I toggle the reset pin, all clock outputs die. Ideally, I would like to use one of the PLL's outputs for an FPGA so that I can perform a synchronization routine on a Phase aligned and Phase-locked system across 2 different boards.
- Is it possible to reset specific output dividers versus all at once?
- I attempted over SPI to turn off an output divider and re-enable it to achieve the above, but this causes the PLL to lose lock.
3) Turning off a PLL output divider counter over SPI and back on again causes the PLL to lose lock. The PLL will only re-acheive lock with a hard reset.
- This is the only way I could think of aligning specific outputs while keeping the main FPGA reference alive to the locked external clock. Is there a way to do this?
Are there any application notes or methodologies for how to lock and align multiple remote CDCE72010's with each other?
