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Part Number: CDCE72010
Hello, I am working with an Abaco FMC150 reference design and am having problems synchronizing multiple CDCE72010 devices with each other.
I can see that the multiple PLLs are achieving lock, and their generated clocks are phase-locked with each other, however:
1) Even though the generated clocks from PLL-1 and PLL-2 are phase-locked, the output divider counters are out of sync, and thus the generated clocks are not phase aligned.
- If I toggle the RESET pin synchronously on the PLL's, I can get the phase on PLL-A's clocks to be in line with PLL'Bs clocks some of the time other times, the output clocks from A to B are 180 degrees out of phase.
2) When I toggle the reset pin, all clock outputs die. Ideally, I would like to use one of the PLL's outputs for an FPGA so that I can perform a synchronization routine on a Phase aligned and Phase-locked system across 2 different boards.
- Is it possible to reset specific output dividers versus all at once?
- I attempted over SPI to turn off an output divider and re-enable it to achieve the above, but this causes the PLL to lose lock.
3) Turning off a PLL output divider counter over SPI and back on again causes the PLL to lose lock. The PLL will only re-acheive lock with a hard reset.
- This is the only way I could think of aligning specific outputs while keeping the main FPGA reference alive to the locked external clock. Is there a way to do this?
Are there any application notes or methodologies for how to lock and align multiple remote CDCE72010's with each other?
I'm looking into it and will get back to you soon.
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In reply to Hao Z:
I went through the datasheet and didn't really see output synchronization feature across multiple devices. Could you share where you got the idea that the outputs of multiple parts can be phase aligned?
So theoretically when there's a /2 frequency divider, there are two phase possibilities. The two possible options have 180 deg phase difference. If it's /4, then there are 4 possibilities, and the phase difference of these four options is 90 deg. Same is true with /8, /16...
Internally, the initial states of all 8 frequency dividers are aligned so that all outputs are phase synced even when output dividers are used. However, there's no guarantee that the initial states of divider flip-flops are aligned across multiple devices unless there's some kind of "SYNC" pin or "SYSREF" pin for JESD204B standard, in order to achieve deterministic latency. Correct me if I'm wrong, but I don't see these features being mentioned in CDCE72010. You probably need to consider parts such as LMK04832.
I inherited a half complete design from an engineer no longer at this company. That engineer mirrored the HiTech Global design for an FMC150 radio transmit and receive board which comprises of these three primary parts:
CDCE70210 for clocking
ADS62P49 for radio Rx
DAC3283 for radio Tx
All three parts are controlled by a Xilinx Zynq FPGA SoC
The FMC150 design was also not intended to be synchronized together and thus I am painted into a corner trying to get this to work. As the acting design engineer on this task, I need to evaluate if we can rework this topology with a simple board respin and FPGA code modification or scrap the entire design altogether and start from scratch...
I have had some success in bringing in a separate synchronizing clock to each individual Zynq FGPA, and having the FPGA perform a bootup-synchronizing routine to pull the CDCE70210's in and out of reset at the same time.
Will pulling the PLL's into reset together (after they have been configured and while they receive their VXCO clock and external Reference clocks) guarantee that the output dividers start at the same time?
In reply to David Ortigoza:
I'm not exactly sure how this device's output synchronization works. If it's like most of other devices, then the initial states of divider flip flops are fixed. Meaning that if the outputs of both devices are enabled in the same time, then they should be in sync.
Problem is, VDD ramp time or RESET pin ramp time is in the range of a few ms, but period of 1MHz signal is 1us. Also the PLLs of two devices may not lock at the same moment even if the RESET pin ramps up very fast and in the same time.
In general, I'm afraid that this method is unlikely to work. Even if it works, I doubt it'll be consistent over temperature drift.
I see that the LMK04832 device has a separate SYNC pin, which can be used to synchronize multiple remote PLLs with eachother. I will explore using this part and re-spinning our boards with this.
Could you reference me to any similar PLL's that also have a SYNC option so that I can compare? The LMK04832 seems a bit overkill.
Any device with zero delay mode OR a SYNC pin should be able to do the job. I'm not sure about your system requirements but I'm attaching the clock generator portfolio as well as the buffer families. You can choose a clock gen with zero delay mode / SYNC pin or a zero delay buffer depending on your needs. I'll email you a draft version of appnote to help you better understand the synchronization.
Hi, thank you for providing the LMK0482x SYNC appnote, this has helped greatly with prototyping our new clock synthesis scheme out.
I have one last question regarding the language in the CDCE72010 datasheet.
In the dividers table 8 and 12, what does the prime number notation mean?
In other words, what is the difference between divide by 4 (x42) versus 4' (0x0)
There's no difference. Prime only means that it's the second time that number shows up.
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