This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Part Number: LMK03328
To ensure the 10MHz OCXO output stable before the LMK03328 PLLs lock, we add a 10uF cap to the PDN pin.
Most of the time, it power up ok with output clock but not always like that.
We are seeing some of this LMK03328 power up with no output clock at all. By power off then on, it will output clock.
We need to understand why and how this happen? How to fix this issue?
It's less likely to cause trouble if the PDN pin ramps up slowly. It's more likely that the startup time of the XO is so slow that even with a 10uF load, the PDN pin still reaches 1.2V before the XO stabilizes. Please measure the timing relationship between the point where PDN reaches 1.2V and the XO starts to toggle between GND and rail.
Also, increase the capacitance and see if it helps or aggravates the problem. (It should help but if the problem gets worse then lets further discuss it.)
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to Hao Z:
I did several measurements and capture the good and bad results (see the attachments).
In both cases, the 10MHz OCXO output was stable for around 1.5seconds before the PDN reached 1.2V.
In the bad case, no clock output after the PDN reached 1.2V. What cause that to happen and how to fix it?
In reply to Laurie Fung:
I'm still looking into this. The pullup resistor at PDN pin is 200kOhm. With a 10uF cap the time constant is 2s. Meaning that it takes 2s to ramp up to 63% of VDDO_01. I wonder if that's too long.
I'll do some measurement and see what happens if the PDN pin ramps up too slowly and will get back to you later.
In the meantime, can you check the timing relationship between ramping of PDN pin and that of VDDO_01 pin as well as other VDD pins? The PDN pin should reach 1.2V of VDDO_01 after core VDD pins reach 2.72V and VDDO_01 pin reaches 1.7V. Make sure that this condition is met. Also make sure that VDD ramp time is within 100ms as required by datasheet.
VDD does reach 2.72V and VDDO_01 does reach reach 1.7V way before PDN PDN reaches 1.2V. Both VDD and VDDO_01 ramp up much less than 100mS (ramp up around 2 mS).
Please review these attachments. We need to fix this no output issues.
2s time constant may be too long. What is the startup time of the OCXO? Can you add a 4.7kOhm pullup in order to reduce the time constant to 47ms?
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.