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LMK03318: 200/500Hz Loop filter for LMK

Thierry Michelon
Prodigy 70 points
Part Number: LMK03318
Other Parts Discussed in Thread: LMK04832, LMK05318

Hi,

I'm trying to achieve a design with the LMK03318 with a loop filter BW of 200 to 500 Hz for jitter cleaning.

(Phase noise output @100kHz max : -<135dBc/Hz)

I succeeded with the parameters listed below in Clock architect simulator BUT without using integrated loop filter.

I have no success when using integrated R/C since  integrated capacitor values are small.

1) It seems not possible to disable the integrated filter and implement it outside of the chip, can you confirm ?

2) Last possibility I can see is using the register number 120 : When PLL_LOOPBW is 1 the loop bandwidth of PLL is reduced to 200 Hz (jittercleanermode).

But there is no clue in the datasheet about the related loop filter to be implemented when this register is set to 0, can you provide more details ?

Design aimed to be implemented : PLEASE FIND IT IN THE ATTACHED PDF FILE

Thanks for your feedback !

Thierry

DJD_LMK03318.pdf

  • 0
    TI__Mastermind 18070 points

    Hello Thierry,

    You are right. Only third order loop filter (R3 and C3) can be disabled internally (by setting C3 to 0 and R3 to minimum). C2 is already external (see figure 58), But C1 and R2 can only be set internally.

    We have cascaded dual loop jitter cleaners that should be able to meet you requirements easily. They use narrow loop bandwidth for first PLL for jitter cleaning and then normal loop bandwidth for second PLL for frequency planning. LMK04832 is recommended for that purpose.

    Regards,
    Hao

  • 0 in reply to Hao Z
    Prodigy 120 points

    Hello Hao,

    Thank you for your answer.

    - What about using the register number 120 of LMK03318, described p108 and p41 of the datasheet ?

    - Do you have another solution that does not require an external VCO ?

    Best regards,

    Christian

  • 0 in reply to christian fallouh
    TI__Mastermind 18070 points

    Christian,

    I'm not sure what R120 does because loop bandwidth is really decided by charge pump current and loop filter components. I can't think of a way to reduce loop bandwidth without changing those. I'll look into that register but I'd still recommend cascaded dual loop device for jitter cleaning. A newer model LMK05318 has integrated VCOs for both PLLs.

    I'm also attaching the jitter cleaner portfolio: http://www.ti.com/clock-and-timing/jitter-cleaners/products.html

    Regards,
    Hao