LMK05318: 1PPS from gps for create a 640 Hz clock output

Hi Gino,

Apologies for the delay. LMK05318 can accept 1PPS input, and can synchronize OUT7 to the edge of the reference input, using zero-delay mode (ZDM). In ZDM, adjusting the DPLL_REF_SYNC_PH_OFFSET bits can be used to move the phase of the output. See datasheet section 9.3.16 for more information.

The LMK05318 does not have a capability to switch the output frequency on command while maintaining 1PPS synchronization. You will likely need a post-divider and an external mux circuit to choose between the required frequencies. One such implementation could be easily achieved with a dual D-flip-flop configured as a post-divider, setting OUT7 to 1280Hz and selecting either 1280Hz from the LMK05318 or 640Hz/320Hz from the first or second stage of the D-flip-flop chain. You would also need to compensate for the propagation delay, but for straightforward logic circuits this is usually very deterministic and limited to nanosecond ranges.

The LMK05318 can definitely handle a 1PPS reference with ±30ns of jitter. I don't have a number for expected output jitter at this time, but I expect it should be at least better than the input reference (even with a flip-flop divider on the output; small digital circuits are typically very deterministic). Note that for 1PPS, the fractional N-divider MASH engine will add some artificial randomness to the phase of the 1PPS signal, so the DPLL and the APLL should both be placed in integer mode (set the fractional numerator to zero).

Regards,

I changed DPLL BW to 0.01 Hz, and run script. Not verified on board.

1pps_to 1280_DPLL_BW_0p01Hz.tcs