LMX2594: Lock time is 2 to 3 times the simulated lock time

Hi Josh,

I believe the uncertainty comes from VCO calibration. You may need to use full assist to bypass VCO calibration and therefore have a more manageable lock time.

I am now using full assist and still getting a max of 180us lock time when tuning from 15000 MHz to 9500 MHz.  Are there any settings I should check that could be causing a much larger lock time than expected?  The simulation software shows a lock time with assist of 56 us, which is 1/3 of what I'm actually seeing on the board.

To use full assist I am setting bit D14 and D11 of register 08 to 1 and bit D10 or register 20 to 1.  Is there anything else I have to do?

Thanks

Hi Josh,

What is the settling frequency tolerance you used for lock time measurement? For example, +/-1kHz or +/- 100Hz.

I will setup a bench test next week to verify.

I'm looking at a +/-100 kHz window.

Hi Josh,

I measured 13.5µs lock time jumping from 15000MHz to 9500MHz.

OSCin = fpd = 100MHz, default EVM loop filter, CHDIV = 4.

My programming sequence.

1. R16 (VCO_DACISET)

2. R19 (VCO_CAPCTRL)

3. R20 (VCO_SEL)

4. R36 (PLL_N)

At 15000MHz: VCO_SEL = 7; VCO_CAPCTRL = 32, VCO_DACISET = 297.

At 9500MHz: VCO_SEL = 2; VCO_CAPCTRL = 47, VCO_DACISET = 292.

Thanks for measuring that, it gives me hope that I can get the lock time I need.  Was fractional mode enabled?  I know the two frequencies that I'm tuning between are integer-N cases but that was just a test case.  My synthesizer is fractional with a fractional denominator of 20.  Would that affect the tune time measurement?

My programming sequence is R19, R16, R20, R36, R37 (PFD_DLY_SEL), R43 (F), R14 (CP), R0 (FCAL_EN).  CHDIV = 1.

I'll take a look at my setup and make sure there isn't something else masking the tune time.

Thanks for your help.

Hi Josh,

Fractional or integer mode does not matter, the difference is you need to write more registers in fractional mode (fractional NUM). Forgot to tell you, I was using SPI clock of 25MHz, it takes 1µs to write a register. 

Do you really need to change the CP from time to time? If not, then no need to write this register.

R0 is not needed as we are not doing auto-calibration anymore.

Hello,

I got pulled onto something else for a few weeks but I'm back on this.  I was able to get ~ 60us lock time using forced settings.  My state machine takes ~ 14us to run, so I'm at about 46us for the device to lock.  That lock time would be fine but I am also trying to use SYNC and it seems SYNC requires auto calibration and that will again take hundreds of microseconds.  Can I use the SYNC function with the forced settings?

I also measured the lock time of the 15000 to 9000 MHz jump on the eval board for the LMX2594.  The result was ~ 187us and the strange thing was that it didn't matter if I used partial assist, lock time was unaffected.  To use partial assist in TICS Pro I set the frequency to the value I wanted, then I hit the "Estimate Values" button which wrote to the 3 starting value registers, then I toggled FCALC_EN.  Am I doing that correctly?

Hi Noel,

187us was with both partial assist and with no assist.  There didn't seem to be any improvement using partial assist, which was strange.  Also, 187us surprises me because the VCO cal time is supposed to be in the 30 - 50us range so I should only be 30-50us worse than the full assist number.

Right now I'm just trying to verify the tune time measurements from the datasheet on the LMX2594 eval board.  Using Fosc = 200 MHz and Fpd = 100 MHz the VCO cal time should be around 50us.  When I run that test, my tune time is 163us.  We've already shown the loop settling time is small (~ 16us) so my worst case number should be in the ~ 70us range.  

Can you send me the register settings used for the VCO calibration times in the datasheet?  Also, are those numbers in the datasheet taken using the same loop filter as the eval board?

Thanks,

-Josh