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Synchronize two LMX2594s at 4.096GHz possible?

Li Zhang71
Prodigy 90 points
Other Parts Discussed in Thread: LMX2594

Hello there,

I've been trying to synchronize two LMX2594 chips at 4.096GHz.  The output frequency is 4.096GHz before I toggle sync.  However, after I toggle the sync bit toggled the output frequency becomes unstable and shows almost a square wave characteristic.  Since the included divide can only take value of 4 and 6.  How is sync possible for output frequency at 4.096GHz?   The highest VCOband 7 max at 15GHz, with included divide=4 this gives 3.75GHz.  Could anyone from TI confirm whether it is possible to synchronize two LMX2594 at 4.096GHz? If it is possible, what is the correct procedure for synchronization in this case as this is a special case that VCO needs to be divided by 2.  

Let me list my settings for initial configuration

fOsc in is 128MHz, expected VCOband is 1 and VCO should run at 8.192GHz

OSC_2X = 0 (disabled)

PLL_R_PRE = 1,

PLL_R = 1,

Mult = 1 (bypass)

CHDIV = 0 (VCO divide by 2)

PLL_N = 64.

VCO_SEL = 1

MASH_ORDER = 0

VCO_DACISET_STRT and VCO_CAPCTRL_STRT are set according to the formula listed in the datasheet.  

VCO_PHASE_SYNC = 0 and

FCAL_EN = 1.

The above setup gives me the correct frequency output prior to sync. I then tried the following:

After the device is programmed, I then set PLL_N to 16 and VCO_PHASE_SYNC to 1.  Reason setting PLL_N to 16 is because the Included_divide after sync is 4.  

I also tried to program PLL_N = 16 and VCO_PHASE_SYNC = 1 in the initial configuration but that didn't work either.

Thanks,

Li 

  • 0
    TI__Guru* 81310 points

    Hi Li,

    when phase sync is enabled, PLL_N = 16, which is an invalid number. The minimum PLL_N value is 28. See datasheet Table 2 for details.

  • 0 in reply to Noel Fung
    Prodigy 90 points

    Thank you, Noel

    I noticed that it didn't produce the desired outcome when I set the PLL_N = 16 and VCO_PHASE_SYNC =1.  Could you please guide me to sync two LMX2594 at 4.096GHz?

    Li 

  • 0 in reply to Li Zhang71
    TI__Guru* 81310 points

    Hi Li,

    You can reduce the fpd frequency to 64MHz, then PLL_N = 128. With phase sync enabled, PLL_N = 32 and it should lock.

  • 0 in reply to Noel Fung
    Prodigy 90 points

    Thanks again,

    I tried the suggested steps in the lab.

    First, reduced the fpd to 64MHz and set PLL_N = 128. 

    I get the correct output frequency at 4.096GHz prior to enable vco_phase_sync. 

    After setting PLL_N to 32 and enable vco_phase_Sync, the output frequency drops to 3.641 GHz

    Please see the spectrum in the attached picture. 

    I need a clock generation chip that can sync at 4.096GHz for multiple ADCs.  I'm looking at lmx2594 due to the fact that Xilinx's ZCU111 eval board uses this chip. 

    However, I had phase ambiguity issue between two groups of ADCs on that eval board.  I had success synchronizing two LMX2594 at 2.048 GHz in the past but not at 4.096GHz.  

    This goes to my original question whether it is possible to sync two LMX2594 at 4.096GHz.  I would be really appreciated it if you can confirm this.  

    output before sync:

    Output after Sync:

    Thanks,

    Li 

  • 0 in reply to Li Zhang71
    TI__Guru* 81310 points

    Hi Li,

    Short answer is, yes, it will sync at this frequency. 

    Let me check this out in the lab and get back to you in next week.

  • 0 in reply to Noel Fung
    TI__Guru* 81310 points

    Hi Li,

    What is your setting on SEG1_EN?

    I checked this out with my board, with SEG1_EN=1, I have no problem with phase sync, it remains locked at 4096MHz with VCO_PHASE_SYNC = 1.

    IncludedDivide is part of the channel divider, so the total channel divider value is greater than 2 and therefore SEG1_EN should be equal to 1.

  • 0 in reply to Noel Fung
    Prodigy 90 points

    Hi Noel,

    I have SEG1_EN set to 1.  but the problem still exist.  What is your order of register write?  I followed the data sheet to write register from highsst to lowest.  

    Thanks,

    Li

  • 0 in reply to Li Zhang71
    TI__Guru* 81310 points

    Hi Li,

    My test procedure as follows:

    1. TICS Pro --> Default configuration

    2. Make the highlighted changes.

    3. USB communication --> Write All Registers. (PLL will lock to 4096MHz)

    4. Check the VCO_PHASE_SYNC box. (TICS Pro will write R0x24 followed by R0x0)

  • 0 in reply to Noel Fung
    Prodigy 90 points

    Hello Noel,

    Thanks again for your response,

    I found out I mistakenly thought SEG1_EN was enabled because I looked at the register 0x31 instead of 0x1f(register 31) on my spreadsheet.  

    After setting SEG1_EN to 1, I observed 4.096GHz output after program VCO_PHASE_SYNC to 1.

    Li Zhang