I am working on a clock synchronized with a GPS signal. This clock will be the input clock of an ADC.
I am testing the LMK05318 through the evaluation board.
If I apply a voltage divider to the original PPS signal (the amplitude of the signal applied to the EVM is 1.76V), LMK05318 toggles (roughly every two seconds) between the holdover state and the PRIREF state. Even when the PRIREF is valid, both the LOPL_DPLL and the LOFL_DPLL flags are checked (the DPLL doesn't lock to the 1pps signal).
Instead, if I apply to the EVM the original 3.3V 1PPS signal, LMK05318 stays in the PRIREF state until the GPS signal is present and then with a delay (in some cases the delay is 40 seconds) returns in the holdover state. However, also in this condition, once the module has recognized the PRIREF signal as valid, the DPLL doesn't lock to the 1 pps signal (both the LOPL_DPLL and the LOFL_DPLL flags remain checked).
As output frequency I have set 4Hz in order to view better the relationship between the 1pps input signal and the LMK05318 output frequency. However, in the real application the output frequency will be 33kHz.
I attach the two configuration files one for the 4Hz output frequency and the other for the 33kHz output frequency. The behaviour observed is the same for both the frequencies generated
In the evaluation board I am using the standard 48.0048MHz XO.
I have applied to the PRIREF input the 1pps signal coming from the module NEO-M8T.
The other inputs (PRIREF_N , SECREF_P and SECREF_N ) are pulled down through a 1k resistor.
The amplitude of the PPS signal coming from the GPS module is 3.3V.
Is it correct in this case to choose "CMOS" as PRIREF interface type?
At the moment I am using only the amplitude validation option.
However, based on another post present in this forum, I am not clear if I should use the 1PPS Phase Detector validation option.
What else I am missing? Thanks in advance