Part Number: CDCE925
We have a requirement to produce two low jitter master audio clocks that must be locked to a 10MHz input clock.
The frequencies are 24.576MHz and 22.5792 MHz. The solution we opted for was a CDCE913 to produce a 27MHz which then feeds into a CDCE925 which produces the two audio clocks.
The solution works well enough, in that the frequencies produced are 0 ppm accurate, but we have encountered problems with an AES Tranceiver (SRC4392) when we use the synthesised clocks in a specific scenario. Using an alternate clock source into the SRC chip with the exact same settings works as expected, but using the synth clock from the CDCE925 does not.
Looking at the jitter on the synthesised clocks using a 'scope, the 10 MHz input has about 3ns of jitter, the 24.576MHz output of the CDCE925 is closer to 12ns.
We have programmed both the clock synth chips using the values provided by ClockPro. and have no problem with the operation of the chips beyond the jitter on the output.
Is there anything can be done to improve the jitter performance out of the CDCE925? Failing that, can you suggest a better solution to generate these clocks?
If the settings are generated from the clockpro software then I'm afraid that there's not much to be done to reduce jitter. LMK03328 has much better performance. It also has too PLLs.
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