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LMK04832: LMK04832 Sysref Clock problem

Oliver McConnell
Prodigy 160 points
Part Number: LMK04832
Other Parts Discussed in Thread: LMK04828, LMK04821,

On the LMK04832, all the odd numbered clocks are configured as sysref clock outputs like the previous generation LMK04828, but the new LMK04832 outputs much lower amplitude and are much noisier than the device clocks. Changing the clock output to be a device clock gives us our amplitude a signal quality back, but that is not an option for us as we need certain clock to use the sysref divider. The difference is so bad that these clocks are essentially unusable. On the previous versions of the family (LMK04821, LMK04828), this was not a problem with the sysref clocks.

  • 0
    TI__Genius 11900 points

    Hello Oliver,

    What output type are you using and what is the amplitude you are seeing on the outputs? Were there any changes with respect to your frequencies?

    Thanks,

    Vibhu

  • 0 in reply to Vibhu Vanjari
    Prodigy 160 points

    We have tried LVDS with only about 550mVpp amplitude differential. On another output we have tried LVPECL and that only provides about 600mVpp differential amplitude. We are using 10MHz as an output frequency and those low amplitudes are the result. By doing nothing more than changing those outputs to be a device clock, we see full amplitude, but as soon as we change back to a sysref clock, the amplitude is low. Same frequency and output type for device clock or sysref clock. Our device clock output amplitude is 800mVpp differential for LVDS and 1.6Vpp differential for LVPECL as we would expect. Another thing we notice is that when configured as a sysref clock, there is not symmetry between the positive and negative legs of the output so the positive side might be 400mV and the negative side 200mV. On the device clocks, there is perfectly symmetry with 800mV on both positive and negative for LVPECL and 400mV on both positive and negative for LVDS.

  • 0 in reply to Oliver McConnell
    TI__Genius 11900 points

    Hello Oliver,

    Some follow up questions:

    What is your input frequency do you see an improvement in the voltage swing when using a lower or higher voltage divider?

    Is the 10 MHz output at the right frequency?

    Does your Vcc3_SYSREF supply look ok?

    Thanks,

    Vibhu

  • 0 in reply to Vibhu Vanjari
    Prodigy 160 points

    Our reference input is 10MHz to CLKin0 (pin 37 and 38). The output is always the correct frequency. Our power supplies all look good to all pins. I don't know where a voltage divider would be that you are referring to. Is that an option within the chip or are you expecting that physically on board?

  • 0 in reply to Oliver McConnell
    TI__Genius 11900 points

    Hello Oliver,

    Sorry I misspoke I meant the SYSREF clock divider.

    Thanks,

    Vibhu

  • 0 in reply to Vibhu Vanjari
    Prodigy 160 points

    The output amplitude and noise do not change based on SYSREF clock divider.

  • 0 in reply to Oliver McConnell
    TI__Genius 11900 points

    Hello Oliver,

    Are you using the EVM, with default terminations on the outputs? If not can you please provide me information regarding your output terminations. Additionally, if you can provide your register dump, I can check on TICSPro to see if everything is set up correctly.

    Thanks,

    Vibhu

  • 0 in reply to Vibhu Vanjari
    Prodigy 160 points

    This was operator error. I just figured out that I inadvertently set the SYSREF_MUX (register 0x139) to SYSREF Pulser mode. Upon changing that to SYSREF Continuous, it has solved my problem.