Part Number: CDCI6214
The customer set Y4 to LVDS100MHz and checked the waveform on the customer's board.The amplitude is about 0.7V as shown below.
Customers use 0.1μF ceramic capacitor on Y4P and Y4N lines for AC coupled.
The datasheet is descripted about maximum amplitude(DC coupled) 0.45V. Could you tell us why this value is exceeded?
First please make sure that there's 100Ohm across P and N channel or 50Ohm to ground on both. If the amplitude is still too high, then please reduce chx_lvds_cmtrim_inc (R59[12:11]) and/or increase chx_lvds_cmtrim_dec (R59[10:9]). The former register increments LVDS amplitude and the latter decrements it.
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In reply to Hao Z:
Thank you for your comment.
Customer use 100ohm resister between P and N channel.
Also, customer is using AC coupling with 0.1uF. Is it no problem?
Now, chx_lvds_cmtrim_inc (R59[12:11]) is set 00.
Customer will try to increase chx_lvds_cmtrim_dec (R59[10:9]).
In reply to Yusuke Mukuno:
Do you have any comment for below?
>customer is using AC coupling with 0.1uF. Is it no problem?
Also, customer tried to increase chx_lvds_cmtrim_dec (R59[10:9]).
However, LVDS output amplitude is not improved.
Could you please give your advice?
Also, could you please give me your comment for below?
>>Customer is using AC coupling with 0.1uF. Is it no problem?
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