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LMK05028: Output phase synchronization to input 1PPS

Part Number: LMK05028

Hello,

My goal is to create synchronized low frequency clock (1Hz, 100Hz. 1000kHz) on 2 (or more) different cards, using a 1PPS signal from GPS module at each card

My setup

- LMK05028

- Input 2: 1PPS

- DPLL1: REF-BW 0.008Hz, TCXO-BW 40Hz

- XO 48MHz, OCXO 10MHz +-10ppb

-Output 7: 1Hz, ZDM enable

I want the phase of Output 7 and input 2 is deterministic but I cant achieve that. 

Please help meOUT7_1PPS_ZDM.tcs config the LMK05028 to achieve that.

Thanks

  • Hello, 

    What is the fail mechanism or what do you mean I can't "achieve that"? Is the output phase indeterministic vs. input? So the output phase is moving around? Are you looking at both on an oscilloscope? 

    From your tics file I saw that you had enabled both DPLL1_ZDM_EN and selected DPLL1_ZDM_OUT7, that is correct. 

    Thanks and regards,

    Amin 

  • Hello

    The output phase is lock as figure below. Yellow trace is output 1PPS and the oscilloscope trigger by input 1PPS. Display mode Persistence.

    But, The output phase in-deterministic vs input as the figure below are phase of output vs input at eachpower-up.

    #1 Power-up

    2# power-up

    3# Power-up

    Thanks

  • Hi, 

    Just so I understand better, does status readback indicate phase lock during the time the first image was captured? In persistence mode, while phase locked, the output shifts? Is there any temperature change on the device?

    On images 2 - 4, the output phase is indeterministic, correct? The output comes up at a different location with each power cycle. Has the device phase locked? Zero delay mode phase corrects after DPLL locks. So initial there will be an output, that's indeterministic / random coming out of reset, since as soon as APLL locks output will be available. Once DPLL locks then the output phase will correct to zero delay mode location, that offset should be the same everytime after locking, not the initial offset measured out of reset before DPLL lock. 

    Thanks and regards, Amin 

  • Hi

    In the first image, the readback indicates still LOPL (even after 30 min operation). The output is stable and not moving. Because I use 1PPS from module GPS to trigger and 1PPS from module GPS have +-50ns jitter so it normal.

    Yes on image 2-4 the phase is indeterministic and I can't get the phase lock even after 30 min and the output stable and not moving.

    Can you try my TCS file on your lab or create a TCS file so I can try on my setup 

    Thanks

  • Hello, 

    With the current situation access to a lab is on an extremely limited basis. 

    LOPL issue may be related to detection settings, that's why it's important to monitor the Ndiv and Rdiv brought out on status channel and see whether they're stable and either 0 degrees or 180 degrees phase shifted. When coming out of reset do you observe these signals moving around and then settle into a stable position? Then we can fix the detection levels to make sure LOPL flags respond correctly. 

    If DPLL isn't locked (both phase and frequency lock), ZDM will not be achieved.

    On a separate note, did you set the phase valid threshold level or was that set by the GUI? Currently it's set to the maximum value. If this value is lowered, does your reference get invalidated? 

     Thanks and regards, Amin 

    On main start page, reference validation section:

  • Hello

    I set the T PH_LOCK about 800ns and T PH_UNLOCK about 6000ns as picture below, but LOPL flag can not be clear.

    I monitor the Ndiv and Rdiv and it always 180 degree phase shifted when it come out of reset until the frequency lock (monitor in Frequency counter) 

    I lowered the  phase valid threshold to 500ns and the input still valid.

    Thanks and regards

  • Hello, 

    So Ndiv and Rdiv are 180 phase shifted immediately after reset? There should be some time (measured in seconds) that it takes for it to lock, I don't anticipate it being immediate after reset since it is a 1 Hz input. And there's a note "Until the frequency lock", does something change after frequency lock? 

    Regards, Amin 

  • Also another note, looking at your images again, I need to confirm how they are captured. 

    Again, there will be an initial output that's at an indeterministic offset vs the input. It will come up at a random spot. And if you perform multiple power cycles you will see it come up differently initially every time. 

    Once ZDM is achieved, then the output will correct and move to the spot that it will always be at (give or take) no matter the number of cycles. 

    With the images you have captured, if you're getting the initial capture after reset (or power cycle), then it is expected to be at different places.

    The capture post ZDM correction is where we expected to be at the same sport. 

    Regards,

    Amin 

  • Hello

    Yes they are 180 phase shifted  immediately after reset. I know it weird maybe it make the Phase lock detector not work properly. I tested with LMK05028 EVM before, after reset Ndiv and Rdiv blink out of phase then slowly come in-phase then after about 15min the LOPL is clear. but with our board it cant get LOPL clear.

    After lock the frequency stable and accurate(monitor by Frequency counter Keysight 53220a)

  • Hello

    My oscilloscope set up is:

    - Green trace: 1PPS from GPS module, use as trigger

    - Yellow trace: 1PPS output from LMK05028

    I try to trick it by set the Phase lock threshold to maximum and the LOPL clear then the output phase align close to 1PPS input.

    So i think my problem is setup the phase lock detector. 

    Please setup the EVM and test my TCS file 

     

  • Hi, 

    Please note with regards to 1 pps, the ndiv rdiv will move very slowly, so it may that you have to zoom in to see the stepping/moving.  

    If ZDM is disabled, does that impact LOPL behavior in anyway? 

    And yes, if we can't fix your configuration, then we'll try it in lab with evm but those results may take longer. 

    Regards, Amin 

  • Hi

    Disable the ZDM doesn't impact LOPL behavior

    Please test it with the EVM asps

    Thanks

  • Hello 

    Can you load this 1 pps file and see if DPLL locks? It's not exactly your case but at least we can understand whether there's issue with your setup or not..

    Regards,

    Amin

    3286.IN1PPS_LMK05028_0124B_2019.tcs

  • Hello

    I loaded your TCS file and DPLL is lock, the LOPL and LOFL are clear.

    I see that the Phase lock threshold in your tcs larger than my setup. I think that why my setup the LOPL cant clear. 

    But i think when phase lock threshold should be small such as ~100-200ns depend on the input 1PPS jitter. 

     .

  • Hello, 

    Sorry due to Covid19 getting permission to go into lab has been troublesome, but I will be going into lab within the next week to test out your configuration and hopefully provide a .tcs file that meets your requirements. 

    Regards, 

    Amin