Part Number: LMX2594
I have some questions about LVDS SYNC input as follows.
Datasheet 188.8.131.52 says “LVDS works to 250 mVpp, but is not ensured in production.”.
I do not understand this well.
For SYNC input pin, how much LVDS differential amplitude (Vpp) is required at minimum?
In Datasheet Figure 31, how much ohm is the resistance?
This should be an usual 100ohms LVDS termination?
For LVDS SYNC input, INPIN_HYST should be enabled or disabled?
How to decide disable or enable?
LVDS input Vcm could be what voltage range?
Could it be 0.2V to 2.2V like usual LVDS?
SYNC pulse width could be more than one OSCin cycle?
For example, after SYNC gets high with enough tSETUP/tHOLD to OSCin rising edge, SYNC can stay high for multiple cycle of OSCin period or forever? Or SYNC must be one OSCin cycle pulse?
Q1) This means that the LVDS format at the SYNC input is not specifically tested for in the device test procedure. Using 250 mVpp is a suggestion and can be considered as a typical suggestion, not guarenteed.
Q2) 100-ohm is correct
Q3) I recommend experimenting with this bit in combination with the INPIN_LVL. The default setting 0, is otherwise ok.
Q4) This is ok, please see "7.6.6 SYNC and SysRefReq Input Pin Register". You may also consider changing INPIN_LVL.
Q5) Yes, only the rising edge of the SYNC pulse is critical. Doesn't have to be only 1 OSCin cycle.
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