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LMK04828: Regarding SYSREF_DIV, DCLKOUTx_DIV values

Part Number: LMK04828

Hi,

I am using LMK04828 to generate device clk of 93.6MHz and SYSREF of  2.925MHz ( 93.6/32). VCO frequency= 2995.2MHz. Device clk= VCO_freq/32. SYSref = VCO_freq/1024. I am generating devclk0,sysref0, devclk1,sysref1 in my design. Both the devclks are of same frequency. Both the sysrefs are of same frequency.  I want all the output clocks rising edge to be aligned with each other.

I have 2 questions regarding this.

question 1: If I want all the outputs to be aligned and I dont need any specific delay between them, do I still need to SYNC their dividers? Are the outputs of VCO not phase aligned by default?

Question2: If I use SYNC for the dividers, device clk=vco/32 i.e. DCLKoutX_DIV=32 so DCLKoutX_DDLY_CNTH=16 and DCLKoutX_DDLY_CNTL=16. As per my understanding CNTH and CNTL values should be half of the divider value, is it correct. In case if I want to delay one of the device clk by 1 VCO cycle then CNTL=17 and CNTH=16 for that particular device clk. What if I want to delay one of the device clk by 2 VCO cycles then should it be CNTL=18 and CNTH=16, is it correct??

SYSREF=2.925MHz (VCO/1024) SYSREF_DIV=1024. What should be the SYSREF_DDLY value. Should SYSREF_DDLY be 512 (1024/2)? If not what should be the value. Requirement is device clock and SYSREF rising edges should be aligned. Can you please explain the impact of SYSREF_DDLY value.

Can someone please clarify me with this basic concept regading DDLY values. Thanks in advance.

Thanks and Regards,

sumala

  • lakshmi sumala grandhe said:
    question 1: If I want all the outputs to be aligned and I dont need any specific delay between them, do I still need to SYNC their dividers? Are the outputs of VCO not phase aligned by default?

    Yes, SYNC the dividers.  You can do this by software alone by toggling the SYNC_POL pin with the Normal SYNC setup.  Normal SYNC setup meaning SYSREF_MUX = 0x00 (Normal SYNC).  SYNC_MODE = 0x01 (SYNC Pin).  Note that a pin toggle on SYNC will also cause the sync to occur.

    lakshmi sumala grandhe said:
    Question2: If I use SYNC for the dividers, device clk=vco/32 i.e. DCLKoutX_DIV=32 so DCLKoutX_DDLY_CNTH=16 and DCLKoutX_DDLY_CNTL=16. As per my understanding CNTH and CNTL values should be half of the divider value, is it correct. In case if I want to delay one of the device clk by 1 VCO cycle then CNTL=17 and CNTH=16 for that particular device clk. What if I want to delay one of the device clk by 2 VCO cycles then should it be CNTL=18 and CNTH=16, is it correct??

    The value you program for DCLKoutX_DDLY_CNTH/_CNTL does not depend on the divider value.  This value is relative from one to another divider output.  Suppose all your dividers have _CNTH/_CNTL = 5/5.  If you one one output to be delayed two cycles then that clock can have the value of _CNTH + _CNTL two greater.  So in the prior example, that could be 7/5, 6/6, or 5/7 to have a delay of two VCO cycles.  The minimum off-clock time can be achieved with minimum _CNTH/_CNTL values of 2/2.

    lakshmi sumala grandhe said:
    SYSREF=2.925MHz (VCO/1024) SYSREF_DIV=1024. What should be the SYSREF_DDLY value. Should SYSREF_DDLY be 512 (1024/2)? If not what should be the value. Requirement is device clock and SYSREF rising edges should be aligned. Can you please explain the impact of SYSREF_DDLY value.

    To achieve the same digital delay between device clock path and SYSREF path.  Consider this equation:

    DCLKoutX_DDLY_CNTH + DCLKoutX_DDLY_CNTL  = SYSREF_DDLY (global SYSREF delay) + SDCLKoutY_DDLY (local SYSREF delay) + SYSREF_DIV_ADJUST + DCLKout_MUX_ADJUST

    By aligning these numbers, the device clock and SYSREF clock would approximately share rising edges.

    Where SYSREF_DIV_ADJUST is

    SYSREF_DIV % 4 SYSREF_DIV_ADJUST
    0 2
    1 2
    2 3
    3 3

    And DCLKoutX_MUX_ADJUST is...

    DCLKoutX_MUX SYSREF_DIV_ADJUST
    0 (Divide) 1
    1 (Div + DCC + HS) 0

    73,
    Timothy

  • Hi Timothy,

    Thank you very much for your detailed reply.

    So based on your reply, If sync is not provided , VCO outputs won't be phase aligned. Am I correct?

    In "section 9.3.3 Digital Delay" of LMK04828 datasheet

    In both delay modes, the regular clock divider is substituted with an alternative divide value. The substitute divide
    value consists of two values, DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL. The minimum
    _CNTH/_CNTL value is 2 and the maximum _CNTH/_CNTL value is 16. This will result in a minimum alternative
    divide value of 4 and a maximum of 32.

    Based on this I thought the DCLKoutX_DDLY_CNTH/_CNTL to be half of the divider value.Can you please tell what the above statements mean? 

    Thanks and Regards,

    sumala

  • Hi Timothy,

    Thank you very much for your detailed reply.

    So based on your reply, If sync is not provided , VCO outputs won't be phase aligned. Am I correct?

    In "section 9.3.3 Digital Delay" of LMK04828 datasheet

    In both delay modes, the regular clock divider is substituted with an alternative divide value. The substitute divide
    value consists of two values, DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL. The minimum
    _CNTH/_CNTL value is 2 and the maximum _CNTH/_CNTL value is 16. This will result in a minimum alternative
    divide value of 4 and a maximum of 32.

    Based on this I thought the DCLKoutX_DDLY_CNTH/_CNTL to be half of the divider value.Can you please tell what the above statements mean?

    Thanks and Regards,

    sumala
  • lakshmi sumala grandhe said:
    So based on your reply, If sync is not provided , VCO outputs won't be phase aligned. Am I correct?

    I have always sent a SYNC  pulse to assure the clocks are synchronized, typically I do this with as prescribed on step 2e of 9.3.2.1.1 Setup of SYSREF Example on page 37.

    lakshmi sumala grandhe said:
    Based on this I thought the DCLKoutX_DDLY_CNTH/_CNTL to be half of the divider value.Can you please tell what the above statements mean? 

    In the static digital delay case, if all DDLY CNTH/CNTL values are set to 4/4.  Then all clock will start at the same phase -- no matter what the divider is.  However if one is set to 4/5, or 2/7 or any other combo which adds to 9, then that clock will be one cycle delayed from the other clocks.

    In the dynamic digital delay case, if you are dividing by 8, and DCLKoutX_DDLY_CNTH/_CNTL values are set to 4 and 4.  Dynamic digital delay will have no effect because that's what normally happens during a clock cycle.  4 VCO cycles low and 4 VCO cycles high.  If you want to delay one VCO clock cycle, provided the some of the CNTH and CNTL registers are 9, the rising edge will now be 1 cycle delayed.  Depending on the specific values given to CNTH and CNTL will be your actual waveform.  Note, for dynamic digital delay, it is necessary to program the same DDLY_CNTH/CNTL values into the register following the digital delay register.  In other words, when using dynamic digital delay, with DCLKout0, register 0x101 and 0x102 shall be programmed to the same value and not changed.  The delay adjust happens for DCLKoutX dividers which have DDLYd#_EN = 1 when DDLYd_STEP_CNT register is programmed.

    lakshmi sumala grandhe said:
    Based on this I thought the DCLKoutX_DDLY_CNTH/_CNTL to be half of the divider value.Can you please tell what the above statements mean? 


    The DCLKoutX_DDLY_CNTH/CNTL can be whatever setting you like.

    73,
    Timothy

  • Hi Timothy,

    Thanks a lot for your reply. Now its clear. I need one more clarification for further understanding.

    "In the static digital delay case, if all DDLY CNTH/CNTL values are set to 4/4.  Then all clock will start at the same phase -- no matter what the divider is.  However if one is set to 4/5, or 2/7 or any other combo which adds to 9, then that clock will be one cycle delayed from the other clocks."

    Does this mean, assume clkout0/1/2 are divide by 8. clkout0 settings CNTL=4 CNTH=4. clkout1 settings CNTL=2 CNTH=7. clkout2 settings CNTL=7 CNTH=2. assuming low level is represented by 'a' and high level is represented by 'b'.

    clkout0=  aaaabbbbaaaabbbbaaaabbbbaaaabbbb

    clkout1=  aabbbbbbbaaaabbbbaaaabbbbaaaabbbb

    clkout2=  aaaaaaabbaaaabbbbaaaabbbbaaaabbbb

    So, clkout1 and clkout2 are effectively 1 clk cycle delayed with respect to clkout0 but the first pulse of clkout1/2 won't be 50% duty cycle. Please correct me if my understanding is wrong.

    Thanks and Regards,

    sumala

  • Hello Sumala,

    Actually for the static digital delay case, the output clock remains low for both CNTL + CNTH, then goes into the normal divider operation.

    Only in the dynamic digital delay case do you see the separate low and high counts. You can also refer to the TICS Pro LMK04828 software for the +1 DDLYd registers (like 0x0102) I referred to above.

    73,
    Timothy
  • Hi Timothy,

    Thanks a lotttt for clearing all my doubts. Now its clear. It would have been good if the datasheet had all this info.

    Thanks and Regards,

    sumala