Hi,
I am using LMK04828 to generate device clk of 93.6MHz and SYSREF of 2.925MHz ( 93.6/32). VCO frequency= 2995.2MHz. Device clk= VCO_freq/32. SYSref = VCO_freq/1024. I am generating devclk0,sysref0, devclk1,sysref1 in my design. Both the devclks are of same frequency. Both the sysrefs are of same frequency. I want all the output clocks rising edge to be aligned with each other.
I have 2 questions regarding this.
question 1: If I want all the outputs to be aligned and I dont need any specific delay between them, do I still need to SYNC their dividers? Are the outputs of VCO not phase aligned by default?
Question2: If I use SYNC for the dividers, device clk=vco/32 i.e. DCLKoutX_DIV=32 so DCLKoutX_DDLY_CNTH=16 and DCLKoutX_DDLY_CNTL=16. As per my understanding CNTH and CNTL values should be half of the divider value, is it correct. In case if I want to delay one of the device clk by 1 VCO cycle then CNTL=17 and CNTH=16 for that particular device clk. What if I want to delay one of the device clk by 2 VCO cycles then should it be CNTL=18 and CNTH=16, is it correct??
SYSREF=2.925MHz (VCO/1024) SYSREF_DIV=1024. What should be the SYSREF_DDLY value. Should SYSREF_DDLY be 512 (1024/2)? If not what should be the value. Requirement is device clock and SYSREF rising edges should be aligned. Can you please explain the impact of SYSREF_DDLY value.
Can someone please clarify me with this basic concept regading DDLY values. Thanks in advance.
Thanks and Regards,
sumala