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TI Home » TI E2E Community » Support Forums » Clocks & Timers » Clocks & Timers Forum » About the thermal Pad of CDCLVD1204
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About the thermal Pad of CDCLVD1204

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Jason Gao
Posted by Jason Gao
on Nov 03 2011 20:18 PM
Intellectual540 points

Should the thermal pad of clock buffer CDCLVD1204 be connected to GND? Thank you very much.

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  • mapefer3
    Posted by mapefer3
    on Nov 04 2011 10:13 AM
    Verified Answer
    Verified by mapefer3
    Expert5745 points

     

    Yes, it should be connected to ground as per page 10 of the SCAS898A datasheet.

     

    The device package has an exposed pad that provides the primary heat removal path to the printed circuit board

    (PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a

    ground plane must be incorporated into the PCB within the footprint of the package. The Thermal Pad must be

    soldered down to ensure adequate heat conduction to of the package.

     

     

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  • Jason Gao
    Posted by Jason Gao
    on Nov 18 2011 07:55 AM
    Intellectual540 points

    Thank you.

    You know that CDCLVD1204 is a LVDS clock buffer, but one receiver of CDCLVD1204 is HCSL receiver.

    Could you please tell me how to connect it to HCSL receiver? Thank you very much.

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  • mapefer3
    Posted by mapefer3
    on Nov 29 2011 08:13 AM
    Verified Answer
    Verified by mapefer3
    Expert5745 points

    Hi Jason,

    Sorry for the late reply. Please find attached some examples of interfacing HCSL to LVDS for the CDCLVD1204.

    Best regards,

    MJ7382.HCSLtoLVDS.pdf

    CDCLVD1204 interfacing HCSL to LVDS
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