I see a spec on powerdown is max 4ns risetime.
What is the consequence of a slower risetime?
I understand the divider sync function could suffer from a slow risetime, but I only care that config is loaded from EEPROM when I exit from powerdown.
If this is OK then how slow can the PD risetime be allowed to be?
David, the one risk I see is that a very slow rise time can cause multiple triggering in a short amount of time, which might put the device into some undesirable mode. If the input has a true hysteresis input buffer this should be no problem but I am not sure what the actual CDCE72010 implementation is on this pin. The device characterization has probably only been done with a 4ns rise time signal. I assume the buffer will be fine with slower inputs and I typically don't see issue until you get into the μs rise time range but to guarantuee functionality TI will need to insist on 4ns without simulating and characterizing this parameter further.
Best regards. Falk Alicke
OK, we'll move that pin to an FPGA output. Thanks.
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