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TI Home » TI E2E Community » Support Forums » Clocks & Timers » Clocks & Timers Forum » SPI_CLK input slew rate for CDCE62002, CDCE62005
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SPI_CLK input slew rate for CDCE62002, CDCE62005

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Shahzad Malik97479
Posted by Shahzad Malik97479
on Feb 20 2012 10:22 AM
Prodigy115 points

I am trying to determine the SPI CLK input slew rate specifications for the CDCE62002 and CDCE62005 clock synthesizers.

Also does any inputs include hysteresis? 

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  • Fritz
    Posted by Fritz
    on Feb 20 2012 10:49 AM
    Suggested Answer
    Expert4370 points

    Hi Shahzad,

    the input slew rate requirements can be determined based on the setup and hold time requirements in table 5 of the CDCE62002. Ultimately you need to meet the VIH and VIL condition on SPI_MISO and SPI_LE when SPI_CLK latches.

    The SPI_CLK input incorporates hysteresis (table 1 pin description).

     

    An application note on SPI data transfers can be found here: http://e2e.ti.com/support/clocks/m/videos__files/180965.aspx

     

    Best regards, Falk Alicke

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