Does the CDCM61001/CDCM61004 parts guarantee a phase relationship between the XIN reference input and the OUTP/N pins? If so, how do I know this?
Hi Shahzad,
Unfortunately the CDCM6100x does not have deterministic phase relationship between the XIN reference and the outputs.
Best regards,
Matt
I may be late to address this question. If you are still looking for a clock solution that can provide deterministic phase relationship between input reference and output clocks, I suggest the following low-noise clock generators which support 0-delay mode with internal or external feedback.
LMK03200: 0-delay PLL clock generator with integrated VCO.
LMK04800: Low-noise clock cleaner with dual loop PLLs and integrated VCO. The LMK04800 supports 0-delay feedback in Dual PLL mode as well as Single PLL mode. To support 0-delay and clock phase alignment/synchronization, the clock distribution section also supports programmable digital delay and analog delay for coarse and fine skew adjustment respectively.
Alan