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Clocks & Timers Forum
LVCMOS1.2 clock generation with low jitter
We have a self-designed digital-to-analog converter (DAC) requiring 1.2V/0V clock signal up to 300MS/s. Our DAC has 15-bit resolution, so we also want the clock to have low jitter performance. We would like to put some clock generation chip on board for this purpose. Does any of TI part have this functionality? I have been looking around TI products. It seems that none of the parts can support LVCMOS12 output. Does anyone have suggestions on parts for clock generation in our test case?
thanks for your interest in TI - clock products. In order to better address your request, I would need some additional information about your DAC: what is the DAC bandwidth? what is the SNR your system requires?
About your question about the 1.2V LVCMOS output, we could apply a resistor divider at the 3.3V output of the clock synthesizer and reduce the amplitude to 1.2V. This solution will work as long as a 3.3V supply voltage is available on your board.
Our DAC output bandwidth is around 150MHz, and the SNR we would like to have is between 85dB and 90dB. If we use the resistor divider, will that and parasitic caps destroy the speed of the clock? Also, what is the jitter performance after applying the resistor divider? I was thinking of using clock distribution buffer such as CDCLVC1310 or LMK00101. Could you please comment which solution will better suit our case?
you need definitively an high performance clock generator. You may choose between the CDCM7005 or LMK04xxx Family device. If you want to use a buffer, I would rather suggest to set the frequency synthesizer outputs to LVPECL and let them to get converted by the clock buffer. The CDCLVC1310 and LMK00101 have similar jitter performance. The slight difference is about the current consumption: the CDC has lower core supply (VDD) current than the LMK,but the current for output buffer supply (VDDO) is lower for the LMK than for CDC. Please notice than the min VDDO is 1.5V for both buffers.
Thank you very much for your reply and recommendation for parts. To get 1.2V clock signal, you were talking about using a voltage divider. Does it affect the speed or jitter performance of the generated clock? Can we use this solution in our case for such high performance clock generation? Could you please comment on it a little bit more?
If you use a voltage divider, use small resistors so that the frequency of the pole set by the parallel resistance and parasitic capacitance doesn't cause much degradation of the clock's edges and thus impact jitter. The LVCMOS clock driver will need sufficient output current to achieve the required output swing with a heavy load.
Also, if your clock driver is not so close to your destination device, then you should also properly terminate the transmission line. If you design your lines with 50 ohm characteristic impedance, then you should use a 50 ohm load termination.
The LMK04800 or LMK04000 family of clock generator's LVCMOS outputs can sink/source 28 mA with output swing up to 1.65 V (Vcc/2). With a 50-ohm load, the output can swing to 1.4 V.
The LMK00101 and LMK00105 LVCMOS clock buffers can drive a 50-ohm load with output swing near Vddo/2 over frequency as shown in the plot below from the datasheet.
I want to generate a 1.2 V 250Mhz clock, I search from the website, the voltage level translator can not support such high bit rate(500 Mb/s). Could you give some suggestions? Could I also use the voltage divider? If yes, is there any simple clock generator you recommend? Since I only need one channel clock. Thanks.
I answered this question in your other forum post:
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