The CDCE706 datasheet in Fig. 10 shows (correctly) that on the SMBus the bus master outputs a not-ACK (high level) after the last read byte being received in, just prior to the Stop (P) signaling at the end of the bus transaction.
The sloa132.pdf application report ("SMBus Compatibility With an I2 Device") however does not indicate this, and appears to be (grossly) in error, as Fig. 3 shows (incorrectly) that the final master-produced ACK bit in a read transaction is low (an "ACK"), while it should in fact be high. The application report required correction.
There is furthermore a question then regarding the accuracy of the CDCE706 datasheet in Fig. 8, where it is indicated that the bit following the read data byte can be either an ACK (low) or NAK (high). This is in contrdiction with the I2C and SMBus specs, that again indicate that that bit needs to be high. Pleaase clarify whether for the CDCE706 Fig.8 is or is not correct. If not correct, the datasheet requires correction.
Note that the issue(s) here likely extend (far) beyond just the CDCE706, possibly affecting all TI devices having I2C/SMBus interfaces and their associated product documentation.
Thanks for making us aware. We will review and do the correction where needed.