This dual fractional N / integer N IC was chosen as the contender for this project, being the only device that could be used for its functionality at frequencies at 50 MHz to 1GHz.
It is used in fractional N mode to realize the required phase noise with the loop bandwidth to achieve the necessary frequency jump and lock time and provide frequency “kick” immunity during TX ramp up and down.
When we started development we used samples that had VM92AB code on them.
The IC performed to the design. Now at present we are starting to see an increase in the time to lock for similar frequency jumps as measured in development.
This is disconcerting as the degradation is much worse than is possibly allowed ie a reduction of about 20MHz in frequency jump and lock.
Using an older IC in the circuits that fail remedies the failure and the original performance is obtained.
The charge pump is programmed on change of frequency to be used at maximum current output then reduced to a steady state to achieve the required ssb phase noise performance.
The PD frequency is about 2.14MHz and the design requires at least 1.5mA as cp initially .
A test jig was set up where the cp output was taken to gnd and then the VP supply by a1kOhm resistor to measure the current.
On the earlier “good” samples the current measurement indicated by the voltage drop across the 1kOhm resistor when pumping shows symmetrical current of about 1.55mA to 1.599ma.
The supply pin in all cases is 2.99Vdc.
With the current devices the date code VM18AB the current measured is asymmetrical with positive 1.3mA and negative -1.26mA.
This is very soft and shows about 19 to 20% low from the data sheet..
Its also of concern that if the cp current is soft is it an indication that this may cause premature field failures?
This is a lot to process, so let me address some individual issues:
1. The IC performed to the design. Now at present we are starting to see an increase in the time to lock for similar frequency jumps as measured in development.
-> The lock time is mainly governed by the loop bandwidth. The loop bandwidth is mainly governed by external components. If the VCO is also different, this is likely to be a cause because a difference in the tuning gain or linearity of the VCO could impact your lock time. I have seen this happen before.
As for our device, the only things I could think of are:
a. Fastlock/CSRC Disengagement glitch
When the charge pump is changed when the device is changing frequency, such as the case for Fastlock or CSRC, there is a disengagement glitch. Now this glitch does degrade the lock time from what one would theoretically expect from these, but still are a benefit. For instance, if I use a 16:1 fastlock, I can theoretically get a 75% reduction in lock time, but I might only get 50% reduction due to the glitch. I could see this glitch changing and if the timing of this glitch is far too early or too late, then it could make the lock time different for different date codes. For this, you might try for diagnostic purposes to not use any fastlock/CSRC and see if date codes are still different. If they are not different, then it points to a fastlock glitch and we can focus on the timing of the disengagement.
b. Power on reset
If you are coming out of a power down reset and not resetting the counters, this could introduce some differences.
Now as for the charge pump current, I do not think that you are measuring the true charge pump current. To measure this current, you need to be sure that the charge pump is always on and never turns off. Even if you remove the OSCin or FinRF signals, these counters can still self-oscillate and prevent you from getting a true measurement of this current. To get a proper measurement, you need a signal applied to one of these pins and the other needs to be put to a DC bias voltage to prevent self-oscillation. If you are not doing this, the self-oscillation could be what is causing the differences and lower currents.
Note that self-oscillation ONLY occurs when there is no input signal.
I would be concerned that there is no min/max spec for Charge Pump current out as this affects capture range and loop stability. only Nom = +/-3.5mA?
Then you need to ensure overall loop design is stable over tolerance of Vdd, Temp and chips 3sigma
Is there a difference in IcpOut among LMX2485CE vs LMX2485E vs LMX2485?
EE since 1975 It's just a simple application of Ohm's Law . .. Former employee of Bristol Aerospace, Interdiscom, Burroughs/Unisys, Iris Systems, C-MAC ....
I do not know of any LMX2485CE. But the LMX2485 and LMX2485E are the same. In fact, the entire LMX248x family has the same charge pump and currents.
We do not have a test limit in the datasheet, but we do show variation over tuning voltage.
Indeed, if the charge pump current varies, this can impact the loop dynamics. But also, the VCO tuning gain can also vary and impact this, and typically the VCO tuning gain variation is more than the charge pump variation. This is not a guarantee, but a pessimistic assumption might be the charge pump current could vary +/- 20%. Now the VCO gain could also vary, so you need to add this variation on top of this.
If you design for lower order filters and/or higher phase margin, these filters tend to be more tolerant to variations in the charge pump current and VCO gain.
I never found the subject of this thread either...LMX2485CE...
In general a good PLL design must have a capture range that exceeds the offset from all sources of variation.
So one must do a margin budget and calculate margin for capture range.
Often the dual range loop accomplishes this. Alternatively and F/P mixer can be used to switch modes to have infinite capture range in F mode and then switch to phase (P) mode for low jitter.
The LMX2485 phase frequency detector has infinite pull-in and infinite hold-in range. However, the filter can still be unstable due to the poles of the closed loop filter being in the right hand plane or the loop bandwidth getting too wide relative to the phase detector frequency. Typically, the gain needs to be far off (i.e. >2x to cause the kind of problems).
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