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Rudolf,

Consult with a Xtal design manual.

 When Xtals are used with CMOS in parallel mode, the load capacitance sets the initial freq.  at room temp.  This can be trimmed by adjusting your on board values of C1 & C2. in a PI shape filter such that series equiv cct of 2 caps = Load Cap of say 15 or 30 pF. In your case it does not matter, but for VCXO, it might.

More importantly what is your overall budget for error.?  +/- 25ppm is just initial error at room temp,

There is also a temperature error that can be +/- 50ppm depending on range or less and aging factor of 5.

So in general I would call this part a 25/50/5 ppm xtal unless specified with more details which are lacking on temp.  ( ie 125ppm error in 10 yrs)

If error is not significant, any Cap value wiill work, needs cap in design to meet 25ppm. otherwise it is will run higher.

Tony

EE since 1975

Hello Tony,

thank you for the reply.

If I got it right, you suggest to run this SPXO with maximum allowed capacitive load to achieve maximum accuracy. I'm not sure, the XTAL and oscillator circuit are integrated, so load should not influence the output frequency?

But if it has an effect on frequency, then I could optimize this by summing the board capacitance, CDCLVC1106 capacitance and an additional capacitor. Right?

My question still remains, what is the input capacitance of the CDCLVC1106? Is it negligible? I found nothing about it in the datasheets.

Rudolf

Yes I was referring to the tuned caps that load the crystal to bring it within specified room temp freq of +/25ppm

These caps would work ok for the 15pF Xtal and the clock buffer is good practice to avoid edge glitches from circuit noise.

Use this or any equivalent CMOS chip. Some prefer UB or unbuffered for Xtal which have a gain of x10 and others simply dont care and use standard buffered inverters with 3 stages , hence x1000 gain which can make it sensitive to some xtal overtones or noise glitches.

Trust but verify your design over whole supply range and with heat gun and cold spray.

YOu dont need that big CLock buffer chip to drive the FPGA. Just use another inverter in the same package as the oscillator.  HC04UB or whatever.

Unless you need have many clocks to distribute with " Very Low Pin-to-Pin Skew < 50 ps "  :P)  

which I seriously doubt.

Hello Tony,

I will go with the integrated XO and clock distribution chip. Have followed your advice and send an inquiry to the XO manufacturer about frequency tolerance over the operating temperature range.

Thank you.

Rudolf

Hello Julian,

these ~2pF sound good to me. Board capacitance will be far below 2pF (trace length <1cm). So I think 15pF XO should be enough.

Thank you.

Rudolf

I agree with Rudolf, Although I am accustomed to selecting the best Xtal supplier for the best price< $0.25 and choosing the discrete cap values as I showed previously.

 I didn't look until now and to see your Xtal spec is for an XO not just X so that is already done for you, so it is just a matter of fanout load. Since TI nor JEDEC state the input capacitance, we can compare with other LVCMOS vendors.  MOT says their part is 4pF nominal Cin and this will be controlled by Vss and batch tolerance. .  Mot spec is for Xtal not XO but of course either will work on their clock chip. http://www.onsemi.com/pub_link/Collateral/NB3H83905C-D.PDF < note Cin.

Make sure you follow the 50Ω transmission line in your layout and if you want to minimize FCC emissions, put guard ground tracks on either side in your microstrip design or either layer for a stripline design and use appropriate ferrite sleeve or feedthru's on external interface signals and design everything to the Automotive standards for Polarity reversal, overvoltage and load dump.

After all this is done 15pF load option should be OK.  I suspect that affects their choice of driver series  or push resistor value for driver impedance. 

I meant that I agree with Julian and Vss should be Vdd which rises for lower voltages, I believe. but still moot point.