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CDCE72010 SPI Problem
I have a PCB with a CDCE72010 clock synchronizer on it but the SPI communication doesn't work. Probably i do something wrong on the master side or the hardware desing is faulty but i can't figure out what could be the problem. General troubleshooting steps have been done (check power pins, check signal levels etc) and the ic have been replaced once also.
Here are oscilloscope screenshots from three consecutive read requests: (signals are LE, MISO, MOSI, SCK)
I issue a read command with 1110 (zero first) followed by the address 1100 and 24 0s. Than i pulse LE and send 32 clock pulses for incomind data. Can anyone tell me whats wrong with this?
It might be simple but i'm working on it now for more than a week and i'm really tired of it. Any help would be highly appreciated.
Sorry for the delay on this post, I'm sure you've found the answer by now but maybe this will help others...
"Please check the second set of clocks after issuing a read-the picture shows only 31 edges before LE is pulled high. This may be why consecutive reads give different results. Try to modify your code to insure 32 edges within each LE cycle." (answer courtesy of one of TI's apps engineers)
Hope this helps.
Thanks for using the forums!
It is not the strongest of the species that survives, nor the most intelligent that survives. It is the one that is the most adaptable to change. - Charles Darwin
Thanks for your reply. Meanwhile i got response from e-mail tech support also. Unfortunately the real problem is caused by something else. It's my fault that i've uploaded the wrong screenshot that shows one of my 1 million trys. The CDCE72010EVM eval board has also arrived, and i've checked the signals, but everything is like i thought it should be but still not ok on my board. I have the proper input signals but still wierd output depending on address and previous input.
The difference between the eval board schematics and my own is that i have most of the outputs unconnected. POWER DOWN# and RESET# also unconnected (datasheet says those have internal pullups). TESTOUTA and STATUS unconnected. I don't need those. And VBB also unconnected. On the eval board there is a bypass cap on the latter which i've missed. Is that crucial?
Does the device requires some kind of startup action like pulsing RESET# or sg? I can't find that in the datasheet. My other guess is that during power up accidentaly a rising edge on the CLK line occurs while LE is low. Can that affect communications after pulsing LE?
Tomorrow i'll try to connect the SPI output of the eval boad to my CDCE72010 and see what it does, but i'm expecting similar results. Any other hardware troubleshooting tips regarding the serial interface of the CDCE72010 would be highly appreciated.
Thank you very much!
p.s.: Sorry my english is not perfect
Your English is just fine!
In regards to your questions:
At power-up LE should be tristate or high or the device might go into a test mode or CD mode. But in this case, the device will not operate right...
Do you know if the device is operating correctly or where you are able to get the device to work? Are you getting intermittent communication errors? That might be causing the problem...
The apps engineer would like to know the frequency of the SPI-clock and the lengthe of the SPI-Bus to see if you are running into a signal integrity issue.
Hope this helps!
I've connected the SPI lines of the eval board to my cdce72010 and it works. Probably there is some kind of startup issue but it's not very important right now since i can configure the ic confortably through the eval board. However i still have other problems. Would you be so kind and ask the apps engineer to look at this again?
So output dividers works fine. I have a 400MHz Vectron VCSO on the VCO input and the divided frequencies are present on the desired outputs. However i can't make the PLL lock on the reference frequency. The CP output not works as it should i think. On the eval board if i disconnect the referece the CP output goes to GND or VCC depending on the polarity set, but on my board it is always near GND expept if i force it to VCC/2. In test mode i can set it to sink or source but no change in normal operation. I've tried also removing my loop filter but got same results. My guess here is some damage in the ic because components were replaced around it several times since it have been soldered in due to SPI problem. Unfortunately i can't replace the ic again because the firm where we assemble our boards have their holydays and will open only in january. Until then i'd like to filter out any potential mistakes so i can make it work fine on the first days of the new year.
Thank you in advance!
Bagoj - I'm still waiting to hear from some of the apps team, I think most are out on Holiday. I will follow-up with them as soon as I can. I hope this is OK.
Today i've had the ic replaced again. Now the charge pump works also as should. The loop is locked, so it works fine. :) Thank you for your help so far.However there are still some issues i don't really understand so i might ask futher questions in the future.
I'm happy to hear things are working! Sorry we couldn't get you there sooner. Please post here if you have any further questions.
Happy New Year!
Hope you had happy holidays. Now i'm back with another CDCE72010 related question. I still haven't dealt with the spi issue, since the eval board is just fine for programind the part now, but i'll fix that later, i think that won't be a problem. However...
I've tried to set up configuartion default mode and i've encountered some strange behaviour again.I have a 400MHz VCO connected to the ic, in SPI mode everithing is fine. Output 0 is an LVCMOS output, output divider #1 set to 5, so i have a 80MHz output. My boss requested it to be switchable between 80MHz and 100MHz.. (Of course if i set Ouptut divider #1 to 4, 100MHz is present on the output.)
I've set output diverder #2 to 4 (100MHz). In Register #1 bits 22 and 23 (DIVPHA1CD1H and L) is set to 01, 10, or even 11 i can't get 100MHz output. I've checked CD1 operation, if i can switch on and off output 0. If i set Register #0 bits 24,25 (OUTBUF0CD2LX and Y) to 00 (LVCMOS) and bits 26,27 to 10 (output disable) it works, i can switch on and off output 0 with CD1 switch. But if i set it to 24,25 = 10 and 26,27 = 00, it is constantly on, and i can't switch it off.
I've also tried some switcing on output #3 that is set to LVPECL but rather than switching off it sets something else (signal level changes). In SPI mode, in the eval board GUI bits are read back fine. Is here something i might miss?SPI cable disconnected, CD mode pin on gnd, CD3 pin on gnd, power off and on: AUX select pin works, REF sel pin works but no luck with CD1 and CD2. I've checked the datasheet for differences in the registers in SPI and CD mode, but found only differences in the last few bits that sets output signal type and divider swapping. Anything else i should set or clear for proper operation? If that helps i can send the register settings saved to a file from the eval board gui.
Please consult an apps engineer if he or she can help me out.Thank you in advance!
I've forwarded your post to a few people, I'll follow-up with them on Monday. Have a nice weekend!
Our GUI does not support CD mode. We don't recommend CD mode as it was only developed for a special request option. Do you really need this mode? If you need a single configuration all you need to do is keep it in SPI mode and the device will boot up in saved configuration.
Does this help?
"We don't recommend CD mode as it was only developed for a special request option."
Well ok, but don't you think you should mention this in the datasheet or something? :) No offense, it's just strange. On the next board we'll have an mcu with spi, so i'm ok with that.
Anyhow, thank you for your replies. I'm glad that this forum exists and this whole community thing. I hope more users and more of your engineers start using it. So keep it up!
That's a valid point, I will pass it on [:)]
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