Cusotmer needs engineering support for his CDCM7005BGA-EVM. Customer states: According to Quick Start model 2-1 of the User’s Guide, The VCXO provided on the Eval PCB outputs 491.52MHz; as suggested we input 61.44MHz @ PRI_REF. In this configuration with power applied D1, D2, and D3 are illuminated and we observe an ≈61.44MHz signal @ Y0A/B which appears to be phase locked to the reference.
I do not know if this output is actually being produced by the CDCM7005 or if it is simply the reference being passed through unaltered. After observing what appears to be valid quick start performance; attempted to control output freq. via the SPI software package downloaded from the TI site. Whenever the send button on the software is clicked the all output from the eval board ceases, and D1-D3 are off. Any configuration of the GUI we have attempted appears to have this effect, including default settings. The RESET button also appears to have no impact. Pushing the PWR DWN button resets the board to the Quick Start condition described above. But any subsequent attempt to manipulate the hardware via the SPI software produces the same result. Phase noise measurements taken in quick start were not what we expected but we assume that this is because quick start is not actually a true indication of part performance.
At this point we assume that these issues are setup related on our end: either due to software considerations such as version, compatibility, operator error, etc, or actual hardware setup, such as jumper settings.
Please provide any amplifying information you feel is applicable, perhaps a loadable setup for the SPI software would be valuable, or screenshots of setups/measurements. Additionally any information regarding expected phase
The input in PRI-REF is not connected to the output. What the customer sees is the VCXO divided by 8, 491.52M / 8 = 61.44MHz. The signal is coming from the VCXO. For a better understanding of the internal clocks please look at page 3 of the CDCM7005 datasheet.
Regarding the EVM and the configuration, the default settings of the CDCM7005 are in pages 22-25 of the datasheet. For the default settings and 61.44MHz input the CDCM7005 should be locked (D1 is ON). That means that the inputs to the PFD (Phase Frequency Detector) need to be aligned.
For the EVM and using the default configuration:
Frequency from PRI_REF coming to PFD: 61.44M / 128 = 480kHz
Frequency from VCXO into the PFD: 491.52M / 8 / 128 = 480kHz
If the customer wants to verify that the CDCM7005 EVM works correctly, he/she can change OUT_MUX_0 = 6, then the output frequency of Y) should be 491.52M / 6 = 81.92MHz.
Finally, find attached the software used to control the CDCM7005 EVM just to be in the same page.
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