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Clocks & Timers
Clocks & Timers Forum
Clock Generation on DM6467
I'm working with audio/video encoder on dm6467 board. In order to achieve correct sync between these streams (on decoder side) i need generate 27MHz PCR and PTS clocks samples. Currently, the clock is being generated by software but syncronism has not been observed. Does my board has a 27MHz clock generator which i can obtain those samples?Does anyone know if there is another way to do this?
Are you using your own custom board?
If not then you can use clock synthesizer ICs to generate synchronous outputs to control the video encoder and decoder. Else, you can synchronize the inbuilt PLLs of DM6467 to synchronize the clocks being generated. If you are using ZTI's EVM, you wont have the privilege of using external synchronizing clock synthesizers though.
Yes, i'm using my own board, more precisely a TI TMS320DM6467.
I read something about PLL of DM6467, but i can't find many docs about it. Nevertheless if i understood what you said, PLLs can "control" frequency inside board devices/peripherals, right?
My problem is that i already have encoded audio e video data as i want, and now i will generate a Program Elementary Stream (PES) and futher a Transport Stream (TS) encapsulating this data. When generating PES, i need stamp PCR and PTS values which will make sync possible on decoder side.
I think that having a clock on DM6467 which i can sampling at software level (my source code) might solve my problem.
Do you know if PLL can be used?
Yes, internal PLL can be used. Normally , it is set to a default value in the GEL file by setting appropriate values of multipliers and dividers to enable maximum frequency operation.
If you look at the datasheet of DM6467, then there is a block diagram which shows the manner in which different SYSCLKs pass through PLL1 and PLL2 to generate appropriate frequencies required for Audio, video , UART etc. You can change those freuqencies by changing multiplier and divider values. But afaik, the sysclk which gets routed to a particular controller after passing through PLL is fixed, and you cannot use another internal clock branch for your own application.
Hope this helps.
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