TI E2E Community
Clocks & Timers
Clocks & Timers Forum
0.8V p-p "clipped sinewave" input to CDCE9xx?
It is very common for precision oscillators to output a "clipped sinewave" signal, 0.7 to 0.8V p-p. By removing a high-current rail-to-rail driver from the oscillator package, this reduces self-heating and improves stability.
The standard recommended circuit to convert this to a full amplitude signal is one inverter, one resistor, and one capacitor. Connect the inverter's output to its input through a 1M feedback resistor to bias it to the threshold voltage, and AC-couple the clock signal in through a small capacitor. (Some oscillators have the capacitor built in.)
That's not very many parts, but in my case, the inverter would be an additional line on the BoM that I'd just as soon avoid.
It occurs to me that the inverter with a large feedback resistor is also the standard Pierce crystal driver circuit used by essentially all chips with Xin and Xout pins.
So I should be able to program the CDCE913/925/937/949 input for crystal mode and couple the signal in through a small capacitor; the inverter and feedback resistor are built in.
I'm wondering if this is known to work, or not to work for some reason that escapes me. Or is a different operating mode preferred? I don't know if the feedback bias resistor is connected in LVCMOS input mode.
The oscillator manufacturer thinks it will probably work if the input impedance is high enough. It's 6 pF and an unspecified resistance; I assume it's "plenty high" (> 1MΩ).
Thank you for any advice!
The CDC3RL02 device was designed specifically for your type of application.
- The output of the integrated LDO can be used to power an external TCXO and at the same time provide some supply line immunity.
- The coupling capacitor is already integrated, elminating the need for the external components that you mentioned.
- Two output channels with separate enable pins provide some flexibility for distributing your clock tree.
- Slew rate control on the output buffers keeps the edge rate between 1ns to 5ns for EMI reduction.
Let me know if this works for you.
Various oscillator manufacturers suggesting that what I want to do is workable (the first explicitly says so):
Thank you for posting this interesting question.
It is possible to use the CDCE9xx series as a clock generator (with PLL on) by connecting a TCXO in the way described in the application notes you are referring to. The Rf internal in the CDCE9xx series is approx 500kOhms, therefore it is not needed to connect one externally.
It would be recommended connecting 1nF in series with XIN and programming the CDCE9xx clock input as XTAL with the minimum internal capacitance load selected. Please note that when the PLL is active the rms jitter for an integration bandwidth of 10kHz to 20MHz would be around 22ps rms. The peak to peak jitter can be as low as 30ps peak to peak for 10k cycles.
For the setup described above please find below the phase noise in Y3.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.