I have a system with 8 CDCE72010 clock drivers. I need to set up all the dividers and then have them synchronized over the entire system. I expect I need to use the nReset hardware input to do this. I don't see how it could work doing it through an SPI command.
I don't see any power down or reset recovery timing in the data sheet. Is there a spec for this? What should I need to do to make sure all 8 of my devices are in synch?
On page 68 of the latest datasheet, there is a list of events that can trigger a SYNC event. This can be done using a SPI command. If you are able to connect multiple outputs from the EVM to an oscilloscope, this allows a good way to view the edge alignment before and after a sync event.
The PDN and RST recovery time is possible to spec to some extent (although it would take me some time to get this data), however there is a significant amount of time afterwards for the PLL to lock which is dependent on input/VCXO frequencies, divider settings, and loop filter configuration. So it can be a little complex to predict this accurately. Fortunately, I don't think it is necessary to use the nRest pin to acheive SYNC.
Since SPI is so vastly slower than my input clock (120MHz) I don't see how I can be confident to get a good sync across multiple systems. I don't think I can even confidently send the SPI command simultaneously.
I am not using the VCO or PLL functions. I have a fixed high precision clock that is input to the VCXO input and used directly in the dividers. I guess this is why I believed the hardware reset line could be used to sync the dividers. There should be no PLL lock issues needing to wait for.
120MHz input to VCXO
1 divider set to 1
1 divider set to 3.
8 dividers identically set to between 6 and 20. (Whatever the choice is they are all the same) These are the ones I MUST have synched across the system of 8 clock chips.
I have been able to sync the dividers by setting reg 6 bit 5 high and using the reset input.
I would like to hear other ways that can work across a large system if you have other ideas.
Do we have an update available?
ACSC Digital Apps
To have a deterministic output on multiple CDCE72010, you would need to elimiate the device delay from input to output. This is called "zero delay" and is done by using the external feeback mode. basically, you want to feed one of your outputs back into the AUXILARY INPUT of the CDCE72010 and set the internal mux to the PFD such that the feedback divider is driven from the AUX input and not the VCXO input.
Best regards, Falk
PS: I forgot to mention: this zero delay tunes out both the CDE72010 delay AND the VCXO output phase uncertainty. If you keep the line length the same from the common clock source to all CDCE72010, and of course also keep all output trace lengths the same, you have a total compensated clock distribution, and the clock phase of the central source is phase aligned to all output clocks.
Thanks for the info. This is fairly bad news for us since all ten of the outputs are used in our system.
It's possible we could move our divide by 1 output to another clock driver, or do without it. If we can use our divide by 3 output for the feedback source as well as the input to a CDCLVD1208 this could work. We would have to route the div by 3 past the AUX input with no termination and then to the 1208 where it would be terminated.
We need 8 divide by 6..12 outputs that must by synced. We have one divide by one that doesn't care about sync. We have one divide by 3 that doesn't care about sync. If we give up one output in order to use the AUX in, we then only have 8 divide by 6..12 and the divide by 3 available as outputs for the feedback.
Thanks, this issue is most urgent.
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