I have another post on syncing multiple CDCE72010's across a system but this question is a little different so I'll put it in a new thread.
My clcok input is through the VCXO pin. I am not using PLL's or VCO, ect. I just run straight off the clock and use the dividers for each output.
If I want to sync to an external signal I set reg6 bit 5 and use the reset input. The only problem is I don't see any spec for reset with respect to the VCXO input clock that can help me determine the timing required to obtain sync on any particular clock edge, or even if it's the rising or falling edge. It is very important to our system to sync properly to a common clock edge.
The only spec I see on reset (and powerdown) is max 4ns risetime.
I just want to be sure I understand - you are using the Reset pin for the sync pulse and want to sync the outputs to the VCXO input?
After the reset pin transitions, the internal sync signal will be asserted and the outputs should synchronize to the next rising edge of the VCXO input. I do not know the exact delay from the reset pin to the sync signal, though it should be very small. This will be in addition to the time between the reset pin transition and the first rising edge on the VCXO input which will vary based on where the reset occurs in the VCXO clock period.
Yes, that sounds like a good description. What is missing is a spec that tells me how to drive the reset to sync on a particular VCXO input clock edge. There must be some setup and hold requirement.
To add further, there is a sync signal sync register that can be used for this purpose, or bypassed for async function. I think I need to use the sync register, but since the must be some setup and hold time for my reset input to the register with respect to the VCXO clock I am in the dark as to how to control this timing.
I also think there is an error on Fig 36 of the data sheet. it shows Reg0(b4) and '1' to select the reference clock, but I want to select the VCXO clock so that would be 'o'. If you look at the Reg0 bit descriptions on pg24, bit 4 seems to need to be '1' to select the VCXO.
Since my reference inputs are both grounded and my clock is on VCXO, I think I need to get that right.
There is also an option of divide by two for the VCXO clock sync input. Does using that improve my reset to VCXO clock setup and hold times any? (assuming I can get a spec for that at all). If it is divided by two, is the actual VCXO edge coming out just going to be random? or is it related to any other control I have access to?
Since there are 8 CDCE72010's in my system that need to sync to exactly the same clock edge, I am hoping the sync timing specs required are realizable across the system from part to part.
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