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Clocks & Timers
Clocks & Timers Forum
CDCE72010 EEPROM Write
I can successfully write the CDCE registers via the SPI bus. However when I try to write these to the eeprom I can't get them to stick. After issuing the write-eeprom command and a power cycle the original values are found.
According to the 0xB bit 26 the eeprom is unlocked, so this should not be an issue. Is there something that I am missing? Is the write - eeprom command as specified in the data sheet? 0x1F?
Thanks for any help.
It looks like you are using the correct command to write the EEPROM. After issuing the write EEPROM command, do you allow 50ms without using the SPI or cycling power for the EEPROM contents to be loaded?
No in fact I was not waiting 50ms. Thanks for the tip. However, since fixing this, I am getting all zeros from the registers after powerup. Only the 0xB bit 27 is high. This is, BTW, with the ads62p48 evm.
My spi interface is implemented with a bit-bang register. Thus the waveform is not necessarily perfectly synchronous. The effective clock rate of the spi clock is very very slow. Could this be an issue?
One thing to check is to make sure the SPI_LE pin is high during power up. If this pin is low, it will prevent the EEPROM from loading to the registers.
I do not think a slow SPI clock would cause an issue as the bit-bang approach is used on the CDCE72010 EVM as well.
Ok, it must have something to do with the SPI_LE pin during powerup. After writing the registers and sending the ram to eeprom command I can verify that the settings are indeed in the eeprom by resetting the cdce with the reset and powerdown buttons on the ads evm. After reset the values are as written. Thus the values must be in the eeprom.
The SPI_LE is driven by my FPGA. I have a pullup on the output (internal to the FPGA) and there is another pullup resistor on the EVM. From my understanding the FPGA pins should be at high-impedence during FPGA loading so in theory the pullup on the EVM should keep the SPI_LE high during loading of the FPGA. After load the internal pullup should only help.
This was exactly the case. At pwr up the fpga is loaded from a flash. During this config time the pin is for some reason weakly pulled down and settles at roughly Vcc/2. I guess one solution would be to try a slightly stronger pullup resistor on the evm. I am working around it now by simply disconnecting the spi_li from the fpga completely (via a jumper on my evm-fmc adapter board.
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