LMX2541SQE2690E OUTPUT FREQUENCY ERROR

Hi,

Is there any update in this query ?. Also for your information for R2_LF i have used 1.8K resistor & in case of evaluation module it is 470 ohms, whether this could be a solution for my issue ?

Regards,

Rajesh

Hi Rajesh,

your register setting is OK, i can make it lock using your setting. Pls note you should program the registers in order.

The reason why freq change after writing to R0 is this register will trigger the internal VCO calibration process. If there existing a valid reference clock, after calibration, it should lock to the desired freq. 

I don't under how did you deal with the LE pin. your spi clock is 6.5MHz, a clock cycle is 154ns, but you said you keep LE low for 80ns. Anyway, could you try keeping LE low all the time when it is not used? that is, follows datasheet timing diagram? I just worry that unnecessary multiple LE H->L->H->L transition will make something wrong.

Hi,

Thanks for the response, I will check your recommendation & I will revert back on this .

I have few quries related to this:

1. Whether R2_LF loop bandwidth resistor will affect my output frequency, because irrespective of register values I am getting 1.5GHz as a default output ?

2. What will be the output frequency if my input clock is not present when i am writing R0 register  & LE toggle?

Regards,

Rajesh.S

Hi Rajesh,

Did you try our Clock Design Tool? this tool is easy to use and it helps you find out the loop filter values and optimize your design.

If you use default evm loop filter value but just change R2 value, both loop bandwidth and phase margin are OK. This issue is not related to the stability of the PLL design.

if there is no valid OSCin signal during VCO calibration, it will calibrate to a wrong VCO freq. When OSCin is resumed, you will notice that the output freq is not correct. A valid OSCin must present before writing to R0, this is specified in the datasheet.

Another thing you may check is the OSCin freq, i.e. the 80MHz signal. Check if it is a precise 80MHz source and its harmonics. You got 1.5GHz at div/2 mode, that means the VCO is actually 3GHz, which is out of our specified range. One possible reason is the OSCin freq is higher than nominal or it locks to the OSCin harmonics. Try set R-counter to 2 to see what happen, if it lock, that means the harmonics of OSCin maybe stronger than the fundamental.

Hi,

Thanks for the reply, I had tried by keeping the LE pin low(as per your suggestion)  instead of toggling continuously. It seems now I can able to generate 1350MHz & PLL is also locking, anyway let me give some time to try for other different frequency.

Regards,

Rajesh