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LMK04806B Single PLL Mode verification

Other Parts Discussed in Thread: CODELOADER, CLOCKDESIGNTOOL

Hello

I am going to design clock solution by using LMK04806B and the target mode is figure2-3 Single PLL Mode - page 5 of LMK04806B data sheet.

I am a beginner to use this device so that want to verify my design is OK or Not.

Configuration is below and configuration file of Codeloader is attached.

Additionally, if the below configurations are effective How much power consumption it needs.

----------------------------------------------------

Reference Frequency: 10MHz

100MHz: LVDS x 1 ch

100MHZ: LVPECL x 2 ch

200MHz: LVDS x 3 ch

200MHz: LVPECL x 1ch

400MHz: LVDS x 3ch

10MHz: LVDS x 1ch

------------------------------------------------

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Reference Frequency: 200MHz

100MHz: LVDS x 1 ch

100MHZ: LVPECL x 2 ch

200MHz: LVDS x 3 ch

200MHz: LVPECL x 1ch

400MHz: LVDS x 3ch

10MHz: LVDS x 1ch

---------------------------------------------------

Thanks and Best Regards

6523.LMK04806B.zip

  • I will review at your CODELOADER configuration settings and let you know soon if the design is OK.

    Did you use CLOCKDESIGNTOOL to calculate the loop filter values for PLL2?

    For calculating power consumption, please refer to the current consumption table in the datasheet and sum the current for the blocks used/enabled for your configuration.

    Regards,
    Alan

  • Hello

    My customer is going to use the LMK04806B and she is reviewing schematic of the EVM BD.

    According to the customer, the schematic is very confused by marking X in red. If you have another reference

    schematic, please let me have.

    Thanks and Best Regards

  • The Red X's in the schematic signify do not populate but can be populated if a particular configuration is desired. This allows the EVM to be flexible for testing and experimentation purposes.

    Gabe