Hello
We are planning on using the following TI clock buffers in a new design:
CDCLVP1204
CDCLVP1212
These buffers will be used to distribute a LVPECL 156.25MHz clock source to multiple 40GBE PHYs and a Virtex 7 FPGA. The source of the clock will be a ultra low phase noise Vectron LVPECL oscillator.
I see that the CDCLVP1204/CDCLVP1212 clock buffers specify a MINIMUM input edge rate of 1.5V/ns. I understand that to get best jitter performance the edge rate should be as high as possible, but why is there a minimum value?
The reason I am asking is because the Vectron oscillator we are planning on using has an differential output voltage level of 0.6V (minimum) to 0.9V (maximum) and a maximum rise/fall time of 1ns. As you can see, this doesn't meet the requirement for 1.5V/ns.
Thanks