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CDCM6208 I2C communication problem

Other Parts Discussed in Thread: CDCM6208

Hi, all!

In I2C mode, what should  I do with unused pins which are SEC_REFx pins and VDD_SEC_REF pin of CDCM6208?. 

It may be a special case peculiar to a customer,,,,,,,
 
1. SEC_REFx pins are left open, and VDD_SEC_REF pin is connected to 3V_VDD.

    - In this case, CDCM6208 sometimes cannot connect with HOST.
      It seems that the I2C timing and ramp-up/down are satisfied with the I2C specification.

    -  When only CDCM6208 is mounted without FPGAs and other ICs on the same PCB,
       CDCM6208 can connect with HOST completely.

2. When VDD_SEC_REF is left open or is connected to GND, CDCM6208 can communicate with HOST  completely.

Regards,
Toshi 

  • Hi Toshi,

    can you send some configuration file, I'd like to reproduce  the issue.

    Regards,

    Ahmed

  • Hi, Ahmed-san, 
    Thanks for your support.

    I am sorry that I did not reply to you sooner..

    Here is a register setting map as below;

    ADRS Data

     0000 01 b9

     0001 00 00

     0002 00 16

     0003 08 F4

     0004 20 EF 

     0005 00 01

     0006 00 03

     0007 00 01

     0008 00 03

     0009 02 03

     000A 00 11

     000B 74 5C

     000C 02 01

     000D 00 3B

     000E 01 EC

     000F 00 01

     0010 00 40

     0011 00 00

     0012 00 01

     0013 00 40

     0014 00 00

    Regards,
    Toshi

  • Hi Toshi-san,

    can you provide schematic for the I2C bus topology as well as the connections for the CDCM6208 device regarding SI_MODE[1:0] and SDA0, SDA1 pins.

    btw. is the above post including schematic and figures related to your issue?

    Kind Regards,

    Ahmed

  • Hi Ahmed-san,

    Does it mean that SDA0/SDA1 is AD0/AD1?
    If yes, here is a part of the schematic that your requested.

    Thanks and regards,
    Toshi

  • Hello Toshi-san,

    I will pick up on this request.

    Best regards,

    Patrick

  • Hello Patrick-san,

    Thanks a lot for your support. I am looking forward to receiving your results.

    Also, what should I do  with unused SEC_REFx pins/ VDD_SEC_REF pin ?

    Best regards, Toshi

     

  • Hello Toshi-san,

    about the unused pins: please connect the VDD_SEC_REF to GND and the SEC_REFx inputs to GND using resistors. If you would like to be able to use the secondary input for eventual debug, then also use a passive to short the VDD_SEC_REF to GND.

    Looking at the schematic screenshot:

    SI_MODE[1:0] = 0b01 => I2C mode - ok

    AD[1:0] = 0b00 => slave address 0b1010100 = 0x54

    Can you let me know how many devices are on the same I2C traces? How long is the net (xx cm)? Is this 3V only or are there mixed power supplies involved?

    When the FPGA is populated is there noise on GND? The device samples the AD[1:0] pin at powerup. maybe it catches different I2C slave address than expected? (You could test by putting kOhm resistor instead of 0Ohm)

    !PDN & !SYNC pulled to GND using 0Ohm resistors. Can you replace using a capacitor? The internal circuit is shown in figure 59 of the data sheet.

    Best regards,

    Patrick

  • Hello Patrick-san,

    Thanks for your  review.
    I will inform your advice to customer.

    About devices on I2C, there are 5 to 10 devices on the same I2C line 
    CDCM6208 is in the most distant position from HOST CPU, and distance is about 30 cm.
    The I2C power supply is 3V only.

    Best regards,
    Toshi

     

  • Hello Patrick-san,

    Customer has an additional question.

    If VDD_SEC_REF is not connected to GND, what impact do you guess?

    Regards,
    Toshi

  • Hello Toshi-san,

    it is just a general suggestion to provide a defined level to the unused circuitry.

    About the I2C issue:

    thanks for sharing the info about the I2C topology.

    Does the customer know the bus capacitance and how the signal looks like at the host controller? Can they determine which type of the transfers is susceptible to fail. Reads? Writes? This can help to debug the root cause.


    Best regards,

    Patrick



  • Hello Patrick-san,

    I could not get the information of the bus capacitance from customer.

    Below is the signal wave form.  
      

    CH1:SCL
    CH2:VCC
    CH3:RESETN
    CH4:SDA

    Their access sequence is as follows;

    w -x a8 0000 01 b9
    w -x a8 0001 00 00
    w -x a8 0002 00 16
    w -x a8 0003 04 F4
    w -x a8 0004 20 EF
    w -x a8 0005 01 10
    w -x a8 0006 00 03
    w -x a8 0007 00 00
    w -x a8 0008 00 03

    w -x a8 0009 1C 03
    w -x a8 000A 00 21
    w -x a8 000B 74 5C

    w -x a8 000C 02 00
    w -x a8 000D 00 3B
    w -x a8 000E 01 EC

    w -x a8 000F 00 00
    w -x a8 0010 00 40
    w -x a8 0011 00 00
    w -x a8 0012 00 00
    w -x a8 0013 00 40
    w -x a8 0014 00 00

    When adding below sequence as dummy write before sending above data to CDCM6208,
    sometimes CDCM6208 can communicate with HOST.

    w -x a8 0003 04 F4
    w -x a8 0003 04 F4
    w -x a8 0003 04 F4
    w -x a8 0003 04 F4
    w -x a8 0003 04 F4
    w -x a8 0003 04 F4
    w -x a8 0003 04 F4
    w -x a8 0003 04 F4
    w -x a8 0003 04 F4
    w -x a8 0003 04 F4
    w -x a8 0003 04 F4
    w -x a8 0003 04 F4
    w -x a8 0003 04 F4

    Regards,
    Toshi