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LMK04828 power supply clock distribution mode only

Other Parts Discussed in Thread: LMK04828, ADC12J4000EVM

Hi,

I will use LMK04828 as a clock/sysref distribution/generation circuit only, no internal PLL nor VCO are used.

Input clock on CLKin1 and all DCLK and SDCLK outputs are used as LVDS.

Actual state of schematic is base on ADC12J4000EVM and DAC3XJ8XEVM schematics.

My questions are about power supply filtering and bypass capacitors:

DAC3XJ8XEVM gives the following power tree:

  1. +3.3VCLK: 33uF, 10uF, 100nF, 7x10nF
    1. Bead => VCC1, VCC2 : 1uF, 100nF, 10nF
    2. Bead => VCC8, VCC10 : 1uF, 100nF, 10nF
      1. Bead => VCC7
      2. Bead => VCC9
    3. Bead => VCC2
    4. Bead => VCC3
    5. Bead => VCC4
    6. Bead => VCC11
    7. Bead => VCC12

ADC12J4000EVM gives the following power tree:

  1. VIO_3P3V_LMK_PLL: 10uF, 1uF, 9x100nF
    1. VCC1, VCC5, VCC7, VCC8, VCC10
    2. Bead => VCC2: 100nF
    3. Bead => VCC3: 100nF
    4. Bead => VCC4: 100nF
    5. Bead => VCC6: 100nF
    6. Bead => VCC9: 100nF
    7. Bead => VCC11: 100nF
    8. Bead => VCC12: 100nF

In clock distribution mode what would be the effect of using a single 3.3V for all VCC?

Can we estimate the power consumption of 3.3V power rail in clock distribution mode?

Thanks and regards

  • Hi Marc-Antoine,

    We are looking at your request and will reply as soon as possible. Thank you for your patience.

    Gabe

  • The power supply tree is taken from the LMK0482x EVM (schematics can be found here http://www.ti.com/lit/ug/snau145a/snau145a.pdf) Because PLL2 is bypassed (also CP2 is not used), R333 can be replaced with a 0 ohm. If OSCin/Out are powered down, then R307, R341 and R345 can be replaced with 0 ohm as well. Depending on your frequency planning, Vcc's for clock outputs can be tied together, but ferrite beads are used for isolation.


    The LMK04828 DS covers current calculations in Section 11. We do not have typical current consumption specs in distribution mode however.

    Gabe

  • Thanks Gabe for your answer.

    About frequencies: Input will be in the range of 500Mhz to 2Ghz, DCLK outputs will be 250Mhz to 500Mhz and SDCLK <100Mhz. For any path, only divider is used (no delay).

    Finally the retained power tree for distribution clock mode only will be:

    VCC for LMK outputs (VCC2, VCC3, VCC4, VCC11, VCC12): each isolated by a ferrite bead and 100nF from 3.3V_LMK.

    VCC for LMK except outputs (VCC1, VCC5, VCC6, VCC7, VCC8, VCC9, VCC10): tied together with 100nF per VCC input, plus 10uF and 1uF on 3.3V_LMK.

    MAS

  • PLEASE PROVIDE CURRENT CONSUMPTION  FOR THE THREE DISTINCT POWER PLANES DESCRIBED IN THE REFERENCE SCHEMATIC (LMK Outputs, pins 10,33,36 and pins 39, 42, 45, 47).  I do understand this current is a function of configuration and would really prefer to use Table 9 in the datasheet but  the datasheet does not specify the power by pin name either and uses some rather obscure references related to function which don't directly translate to current per pin.  The reference schematics are very useful for these parts.  Unfortunately, the power plane section which describes the recommended pin groupings does not show current as a function of the specific pin or even the total group power.  For example how much current does pins 10. 33 and 36 require?Also is this the optimal configuration for minimal phase noise?  

    This information is necessary if one want to size the LDO and choose proper component values based on max currents.

  • This is not perfect information, but in general...

    • All the clock related currents, like output buffer, divider, clock group, etc.  Come from the Vcc supporting that clock group.  This would be the VccCLKoutPlane.
    • The core currents, VCO currents and such come from the VccPLLPlane
    • The VccAuxPlane is for non-device things like the VCXO, VCO.

    73,

    Timothy