CDCE62005 Eternal Clock

Hello Nicholai,

I will start looking into this.

Best regards,

Patrick

Excellent, thank you Patrick.

Have a good day!

Nicholai

Hello Patrick,

I was wondering if you made any progress with this issue? Were you at least able to replicate the problem?

Thank you,

Nicholai

Hi Nicholai,

If I understood correctly, the divider settings are for a 19.2 MHz reference signal not for 15 MHz as you mentioned at the end of your post. Note that the XTAL is not connected to the Secondary input rather the AUX input (for the internal Colpitts oscillator).

Could you please clarify this? Also, the CDCE62005 EVM GUI is capable of generating a device register map for the configuration you seek - I would advise using this took to generate the desired configuration (it also has a register configuration validity check tool built in which returned some errors on your attached register map, mainly on INBUFSELX and INBUFSELY being set to an invalid reserved mode).

Also please take into consideration the input termination required by the device - depending on the coupling scheme, the input buffer can be configured to properly bias in the internal termination. Again, the CDCE62005 GUI should be able to select this.

Gabe

Gabe,

Thank you for your response. The tool I have been using is the GUI tool for the DAC34H84EVM. Apparently this tool doesn't quite cut it, as it seems to be setting the registers incorrectly. I'm trying to get the input source to be primary, not the secondary or auxiliary. 

Perhaps you can help get the settings correctly. I am using a 50-ohm output function generator at 15MHz from 0V to 1.3V set to 15 MHz at the primary input of the CDCE62005. The input is set to LVCMOS. Here is a snippet from the schematic:

I've downloaded the tool you suggested, and have given that a try at generating a configuration file. Note, in the configuration, I have the SEC input set to HiZ, as I do not want to use the on board (on the DAC EVM) 19.2 MHz reference. Instead, I would like to feed the 15 MHz external signal into the PLL circuitry. However, even using this configuration tool, my outputs are still running (right now at 46MHz) when I don't have an external clock connected.

Thank you for your assistance,

Nichoali

Hello Nicholai,

just to confirm my understanding.

you want to replace the fed input frequency, but the outputs shall give the same frequencies as when feeding 19.2MHz. Can you share your frequency plan?

I quickly tried porting the bits from the DAC EVM into our software. I think that the post-divider of the VCO might not fit the VCO range.

update3482.CDCE62005_2014_10_01_E2E_367755_2.ini

please check if the attached fits what you need.

Best regards,

Patrick

Patrick,

Sorry for the delay in my response. At this point, I don't terribly care about the frequency plan. I am troublshooting a noise problem, and thus am trying to eliminate the 19.2 MHz Oscillator as a variable. Its nice to have frequencies in the general vicinity, but what really matters is the frequencies in relation to one another. That is, output one must be 8x output 2, and so on.  My problem, however, is I cannot bypass this 19.2 MHz oscillator for some reason.

Looking at your configuration, I would expect there to not be a stable clock if I don't put an input into the primary. Is that correct? I am not supplying any clock to the CDCE62005, and yet, I'm still getting a stable output clock. This is not what I expect. If I connect an input clock to the device, there is no change in output frequency, even if I change the signal generator from 15MHz to 9MHz to 1 MHz or disconnect it all together- no change at all in the output frequency.

Do you understand my issue?

Patrick,

I think you've answered my question. I think you are correct in that the VCO must just be open. I'm relatively new to programming PLL circuits, and didn't think that the VCO running open was something I needed to worry about. It threw me a little, because when running open, it runs very close to the same frequency when the PLL is locked. 

When changing the frequencies or disconnecting, the PLL_LOCK signal is not on, so that answers the question.

Thank you for your time, I've learned a lot in this discussion,

Nicholai

Hello Nicholai,

your fine. It is hard to find when you do not have all equipment ready. Always good to be helpful! :)

Best regards,

Patrick