Hi,
I'm evaluating LMK04808 with LMK048xx Evaluation Board in dual loop PLL 0-delay external VCO mode using CodeLoader.
The evaluation board mount an external VCO (minicircuits ROS-2490C+), an active loop filter designed with Clock Design Tool and SimPLL used by PLL2 and a 125MHz VCXO used by PLL1.
To test this IC, I provide on CLKin0 a 125MHz clock, set the registers to obtain a PLL1 Phase Detector Frequency of 6250 kHz, PLL2 Phase Detector Frequency of 31250 kHz, external VCO frequency of 2250MHz and an Output Clock on CLKout0 of 125MHz, the EN_FEEDBACK_MUX is active and CLKout0 is selected. The .mac file is attached. 2843.LMK04808_dualPLL_0delay_extVCO.zip
The issue is the following: PLL2 don't lock and the Vtune of external VCO is always stuck at GND.
If I try the same configuration changing only the mode from dual PLL 0-delay external VCO (mode 5) to dual PLL external VCO (mode 3) all PLLs lock, the output frequency is the expected and the Vtune voltage of external VCO is near 7.5V. The .mac file of this configuration is attached. 6521.LMK04808_dualPLL_extVCO.zip
Why there is this difference? From datasheet by looking at Figure 2-2 and Figure 2-1 the feedback of PLL2 with and without 0-delay is equal, in my tests the registers' value is the same and so the external VCO and loop filter is the same, but why PLL2 locks only on mode 3 (dual PLL external VCO) ?
I've tested the dual loop PLL 0-delay with internal VCO modality, generating other frequencies and it works.
